FR2969373B1 - Procede d'assemblage de deux plaques et dispositif correspondant - Google Patents

Procede d'assemblage de deux plaques et dispositif correspondant

Info

Publication number
FR2969373B1
FR2969373B1 FR1060839A FR1060839A FR2969373B1 FR 2969373 B1 FR2969373 B1 FR 2969373B1 FR 1060839 A FR1060839 A FR 1060839A FR 1060839 A FR1060839 A FR 1060839A FR 2969373 B1 FR2969373 B1 FR 2969373B1
Authority
FR
France
Prior art keywords
assembling
plates
corresponding device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1060839A
Other languages
English (en)
Other versions
FR2969373A1 (fr
Inventor
Aomar Halimaoui
Marc Zussy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics Crolles 2 SAS, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1060839A priority Critical patent/FR2969373B1/fr
Priority to US13/330,146 priority patent/US9330957B2/en
Publication of FR2969373A1 publication Critical patent/FR2969373A1/fr
Application granted granted Critical
Publication of FR2969373B1 publication Critical patent/FR2969373B1/fr
Priority to US15/087,093 priority patent/US20160218178A1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
FR1060839A 2010-12-20 2010-12-20 Procede d'assemblage de deux plaques et dispositif correspondant Expired - Fee Related FR2969373B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1060839A FR2969373B1 (fr) 2010-12-20 2010-12-20 Procede d'assemblage de deux plaques et dispositif correspondant
US13/330,146 US9330957B2 (en) 2010-12-20 2011-12-19 Process for assembling two wafers and corresponding device
US15/087,093 US20160218178A1 (en) 2010-12-20 2016-03-31 Process for assembling two wafers and corresponding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1060839A FR2969373B1 (fr) 2010-12-20 2010-12-20 Procede d'assemblage de deux plaques et dispositif correspondant

Publications (2)

Publication Number Publication Date
FR2969373A1 FR2969373A1 (fr) 2012-06-22
FR2969373B1 true FR2969373B1 (fr) 2013-07-19

Family

ID=43629381

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1060839A Expired - Fee Related FR2969373B1 (fr) 2010-12-20 2010-12-20 Procede d'assemblage de deux plaques et dispositif correspondant

Country Status (2)

Country Link
US (2) US9330957B2 (fr)
FR (1) FR2969373B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733300B (zh) * 2013-12-23 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种键合晶片的减薄方法
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
CN108242393B (zh) * 2016-12-23 2021-04-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN109712875B (zh) * 2018-12-29 2020-11-20 上海华力微电子有限公司 晶圆直接键合方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0168348B1 (ko) * 1995-05-11 1999-02-01 김광호 Soi 기판의 제조방법
JP3352896B2 (ja) * 1997-01-17 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JPH11204452A (ja) * 1998-01-13 1999-07-30 Mitsubishi Electric Corp 半導体基板の処理方法および半導体基板
KR100304197B1 (ko) * 1998-03-30 2001-11-30 윤종용 소이제조방법
JP3635200B2 (ja) * 1998-06-04 2005-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP4313874B2 (ja) * 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
US6263941B1 (en) * 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
JP3991300B2 (ja) * 2000-04-28 2007-10-17 株式会社Ｓｕｍｃｏ 張り合わせ誘電体分離ウェーハの製造方法
JP3580227B2 (ja) * 2000-06-21 2004-10-20 三菱住友シリコン株式会社 複合基板の分離方法及び分離装置
JP2003031779A (ja) * 2001-07-13 2003-01-31 Mitsubishi Electric Corp Ｓｏｉウェハの製造方法
EP1507292B1 (fr) * 2002-05-20 2012-05-02 Sumco Corporation Procede de fabrication de substrat, et gabarit de pressage de peripherie externe de plaquettes utilises dans ce procede
US7122095B2 (en) * 2003-03-14 2006-10-17 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for forming an assembly for transfer of a useful layer
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
JP4918229B2 (ja) * 2005-05-31 2012-04-18 信越半導体株式会社 貼り合わせウエーハの製造方法
JP4839818B2 (ja) * 2005-12-16 2011-12-21 信越半導体株式会社 貼り合わせ基板の製造方法
US8119500B2 (en) * 2007-04-25 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding
US8613996B2 (en) * 2009-10-21 2013-12-24 International Business Machines Corporation Polymeric edge seal for bonded substrates

Also Published As

Publication number Publication date
US20160218178A1 (en) 2016-07-28
US20120161292A1 (en) 2012-06-28
FR2969373A1 (fr) 2012-06-22
US9330957B2 (en) 2016-05-03

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Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 6

ST Notification of lapse

Effective date: 20170831