FR2942910B1 - Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur - Google Patents
Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneurInfo
- Publication number
- FR2942910B1 FR2942910B1 FR0951433A FR0951433A FR2942910B1 FR 2942910 B1 FR2942910 B1 FR 2942910B1 FR 0951433 A FR0951433 A FR 0951433A FR 0951433 A FR0951433 A FR 0951433A FR 2942910 B1 FR2942910 B1 FR 2942910B1
- Authority
- FR
- France
- Prior art keywords
- heterostructure
- manufacturing
- reduce
- donor substrate
- strain strength
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
- Light Receiving Elements (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0951433A FR2942910B1 (fr) | 2009-03-06 | 2009-03-06 | Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur |
US13/254,550 US8778777B2 (en) | 2009-03-06 | 2009-09-09 | Method for manufacturing a heterostructure aiming at reducing the tensile stress condition of a donor substrate |
CN200980156845.7A CN102318055B (zh) | 2009-03-06 | 2009-09-09 | 旨在减少施主衬底拉伸应力状态的异质结构体的制造方法 |
PCT/EP2009/061711 WO2010099837A1 (fr) | 2009-03-06 | 2009-09-09 | Procédé de fabrication d'une hétérostructure visant à réduire l'état de contrainte de traction du substrat donneur |
KR1020117020093A KR101302071B1 (ko) | 2009-03-06 | 2009-09-09 | 제공 기판의 인장 응력 조건을 감소시키기 위한 이종 구조체의 제조 방법 |
EP09841026A EP2404318A1 (fr) | 2009-03-06 | 2009-09-09 | Procédé de fabrication d'une hétérostructure visant à réduire l'état de contrainte de traction du substrat donneur |
SG2011060118A SG173788A1 (en) | 2009-03-06 | 2009-09-09 | A method for manufacturing a heterostructure aiming at reducing the tensile stress condition of the donor substrate |
JP2011551420A JP2012519372A (ja) | 2009-03-06 | 2009-09-09 | ドナー基板の引張り応力状態を低減させることを目的としたヘテロ構造を製造する方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0951433A FR2942910B1 (fr) | 2009-03-06 | 2009-03-06 | Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2942910A1 FR2942910A1 (fr) | 2010-09-10 |
FR2942910B1 true FR2942910B1 (fr) | 2011-09-30 |
Family
ID=40627399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0951433A Expired - Fee Related FR2942910B1 (fr) | 2009-03-06 | 2009-03-06 | Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur |
Country Status (8)
Country | Link |
---|---|
US (1) | US8778777B2 (fr) |
EP (1) | EP2404318A1 (fr) |
JP (1) | JP2012519372A (fr) |
KR (1) | KR101302071B1 (fr) |
CN (1) | CN102318055B (fr) |
FR (1) | FR2942910B1 (fr) |
SG (1) | SG173788A1 (fr) |
WO (1) | WO2010099837A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2977260B1 (fr) | 2011-06-30 | 2013-07-19 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiale epaisse de nitrure de gallium sur un substrat de silicium ou analogue et couche obtenue par ledit procede |
FR3051785A1 (fr) | 2016-05-25 | 2017-12-01 | Soitec Silicon On Insulator | Procede de fabrication d'une couche |
US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
RU2633437C1 (ru) * | 2016-08-01 | 2017-10-12 | Федеральное государственное бюджетное учреждение "Национальный исследовательский центр "Курчатовский институт" | Структура полупроводник-на-изоляторе и способ ее изготовления |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2894990B1 (fr) * | 2005-12-21 | 2008-02-22 | Soitec Silicon On Insulator | Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede |
EP1429381B1 (fr) * | 2002-12-10 | 2011-07-06 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de fabrication d'un matériau composé |
US6911375B2 (en) * | 2003-06-02 | 2005-06-28 | International Business Machines Corporation | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature |
FR2856192B1 (fr) * | 2003-06-11 | 2005-07-29 | Soitec Silicon On Insulator | Procede de realisation de structure heterogene et structure obtenue par un tel procede |
WO2006023594A2 (fr) * | 2004-08-18 | 2006-03-02 | Corning Incorporated | Structures semi-conducteur sur isolant contenant du verre/de la vitroceramique a temperature inferieure de recuisson elevee |
EP1782472B1 (fr) * | 2004-08-18 | 2011-10-05 | Corning Incorporated | Structures contraintes semi-conducteur-sur-isolant et methodes pour fabriquer ces structures |
JP5064692B2 (ja) * | 2006-02-09 | 2012-10-31 | 信越化学工業株式会社 | Soi基板の製造方法 |
FR2899594A1 (fr) * | 2006-04-10 | 2007-10-12 | Commissariat Energie Atomique | Procede d'assemblage de substrats avec traitements thermiques a basses temperatures |
-
2009
- 2009-03-06 FR FR0951433A patent/FR2942910B1/fr not_active Expired - Fee Related
- 2009-09-09 US US13/254,550 patent/US8778777B2/en not_active Expired - Fee Related
- 2009-09-09 EP EP09841026A patent/EP2404318A1/fr not_active Withdrawn
- 2009-09-09 KR KR1020117020093A patent/KR101302071B1/ko active IP Right Grant
- 2009-09-09 WO PCT/EP2009/061711 patent/WO2010099837A1/fr active Application Filing
- 2009-09-09 JP JP2011551420A patent/JP2012519372A/ja active Pending
- 2009-09-09 CN CN200980156845.7A patent/CN102318055B/zh not_active Expired - Fee Related
- 2009-09-09 SG SG2011060118A patent/SG173788A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
JP2012519372A (ja) | 2012-08-23 |
WO2010099837A1 (fr) | 2010-09-10 |
CN102318055A (zh) | 2012-01-11 |
CN102318055B (zh) | 2014-04-23 |
KR101302071B1 (ko) | 2013-09-05 |
US8778777B2 (en) | 2014-07-15 |
SG173788A1 (en) | 2011-09-29 |
EP2404318A1 (fr) | 2012-01-11 |
KR20110110369A (ko) | 2011-10-06 |
US20120100690A1 (en) | 2012-04-26 |
FR2942910A1 (fr) | 2010-09-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
|
PLFP | Fee payment |
Year of fee payment: 8 |
|
PLFP | Fee payment |
Year of fee payment: 9 |
|
PLFP | Fee payment |
Year of fee payment: 10 |
|
PLFP | Fee payment |
Year of fee payment: 11 |
|
ST | Notification of lapse |
Effective date: 20201109 |