FR2881273B1 - Procede de formation d'un substrat semi-conducteur de circuit integre - Google Patents
Procede de formation d'un substrat semi-conducteur de circuit integreInfo
- Publication number
- FR2881273B1 FR2881273B1 FR0500674A FR0500674A FR2881273B1 FR 2881273 B1 FR2881273 B1 FR 2881273B1 FR 0500674 A FR0500674 A FR 0500674A FR 0500674 A FR0500674 A FR 0500674A FR 2881273 B1 FR2881273 B1 FR 2881273B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- semiconductor substrate
- circuit semiconductor
- forming integrated
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0500674A FR2881273B1 (fr) | 2005-01-21 | 2005-01-21 | Procede de formation d'un substrat semi-conducteur de circuit integre |
US11/335,857 US7476574B2 (en) | 2005-01-21 | 2006-01-19 | Method for forming an integrated circuit semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0500674A FR2881273B1 (fr) | 2005-01-21 | 2005-01-21 | Procede de formation d'un substrat semi-conducteur de circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2881273A1 FR2881273A1 (fr) | 2006-07-28 |
FR2881273B1 true FR2881273B1 (fr) | 2007-05-04 |
Family
ID=34954337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0500674A Expired - Fee Related FR2881273B1 (fr) | 2005-01-21 | 2005-01-21 | Procede de formation d'un substrat semi-conducteur de circuit integre |
Country Status (2)
Country | Link |
---|---|
US (1) | US7476574B2 (fr) |
FR (1) | FR2881273B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2881273B1 (fr) * | 2005-01-21 | 2007-05-04 | St Microelectronics Sa | Procede de formation d'un substrat semi-conducteur de circuit integre |
US8624349B1 (en) * | 2010-10-11 | 2014-01-07 | Maxim Integrated Products, Inc. | Simultaneous isolation trench and handle wafer contact formation |
US9041105B2 (en) | 2012-07-20 | 2015-05-26 | International Business Machines Corporation | Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure |
Family Cites Families (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2685244B2 (ja) * | 1988-09-30 | 1997-12-03 | 株式会社日本自動車部品総合研究所 | 半導体装置の製造方法 |
JPH02302044A (ja) * | 1989-05-16 | 1990-12-14 | Fujitsu Ltd | 半導体装置の製造方法 |
US6004837A (en) * | 1998-02-18 | 1999-12-21 | International Business Machines Corporation | Dual-gate SOI transistor |
US6476445B1 (en) * | 1999-04-30 | 2002-11-05 | International Business Machines Corporation | Method and structures for dual depth oxygen layers in silicon-on-insulator processes |
FR2795555B1 (fr) * | 1999-06-28 | 2002-12-13 | France Telecom | Procede de fabrication d'un dispositif semi-conducteur comprenant un empilement forme alternativement de couches de silicium et de couches de materiau dielectrique |
US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
JP2001102597A (ja) * | 1999-09-30 | 2001-04-13 | Fuji Electric Co Ltd | 半導体構造およびその製造方法 |
KR100356577B1 (ko) * | 2000-03-30 | 2002-10-18 | 삼성전자 주식회사 | 에스오아이 기판과 그 제조방법 및 이를 이용한에스오아이 엠오에스에프이티 |
US6982460B1 (en) * | 2000-07-07 | 2006-01-03 | International Business Machines Corporation | Self-aligned gate MOSFET with separate gates |
KR100340878B1 (ko) * | 2000-06-28 | 2002-06-20 | 박종섭 | 에스오아이 소자의 제조방법 |
US6429477B1 (en) * | 2000-10-31 | 2002-08-06 | International Business Machines Corporation | Shared body and diffusion contact structure and method for fabricating same |
GB2372631B (en) * | 2001-02-22 | 2005-08-03 | Mitel Semiconductor Ltd | Semiconductor-on-insulator structure |
JP2002299591A (ja) * | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体装置 |
KR100414217B1 (ko) * | 2001-04-12 | 2004-01-07 | 삼성전자주식회사 | 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법 |
US6515333B1 (en) * | 2001-04-27 | 2003-02-04 | Advanced Micro Devices, Inc. | Removal of heat from SOI device |
KR100363332B1 (en) * | 2001-05-23 | 2002-12-05 | Samsung Electronics Co Ltd | Method for forming semiconductor device having gate all-around type transistor |
KR100470832B1 (ko) * | 2002-08-12 | 2005-03-10 | 한국전자통신연구원 | 두께가 얇은 soi층을 이용한 쇼트키 장벽 관통트랜지스터 및 그 제조방법 |
US6717216B1 (en) * | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
US6830987B1 (en) * | 2003-06-13 | 2004-12-14 | Advanced Micro Devices, Inc. | Semiconductor device with a silicon-on-void structure and method of making the same |
US7812340B2 (en) * | 2003-06-13 | 2010-10-12 | International Business Machines Corporation | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same |
US7018873B2 (en) * | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
JP4004448B2 (ja) * | 2003-09-24 | 2007-11-07 | 富士通株式会社 | 半導体装置およびその製造方法 |
US7029964B2 (en) * | 2003-11-13 | 2006-04-18 | International Business Machines Corporation | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
JP2005158952A (ja) * | 2003-11-25 | 2005-06-16 | Toshiba Corp | 半導体装置及びその製造方法 |
US6955988B2 (en) * | 2003-12-04 | 2005-10-18 | Analog Devices, Inc. | Method of forming a cavity and SOI in a semiconductor substrate |
US6943087B1 (en) * | 2003-12-17 | 2005-09-13 | Advanced Micro Devices, Inc. | Semiconductor on insulator MOSFET having strained silicon channel |
US7033869B1 (en) * | 2004-01-13 | 2006-04-25 | Advanced Micro Devices | Strained silicon semiconductor on insulator MOSFET |
KR100612415B1 (ko) * | 2004-04-09 | 2006-08-16 | 삼성전자주식회사 | 올 어라운드된 채널 영역을 갖는 트랜지스터 및 그 제조방법 |
JP4759967B2 (ja) * | 2004-10-01 | 2011-08-31 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100669556B1 (ko) * | 2004-12-08 | 2007-01-15 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
FR2881273B1 (fr) * | 2005-01-21 | 2007-05-04 | St Microelectronics Sa | Procede de formation d'un substrat semi-conducteur de circuit integre |
CN101258590B (zh) * | 2005-09-06 | 2011-03-30 | Nxp股份有限公司 | 带有隔离区的半导体器件制造方法及该方法制造的器件 |
JP4644577B2 (ja) * | 2005-09-30 | 2011-03-02 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
JP4940797B2 (ja) * | 2005-10-03 | 2012-05-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7659172B2 (en) * | 2005-11-18 | 2010-02-09 | International Business Machines Corporation | Structure and method for reducing miller capacitance in field effect transistors |
JP4792957B2 (ja) * | 2005-12-14 | 2011-10-12 | セイコーエプソン株式会社 | 半導体基板の製造方法及び半導体装置の製造方法 |
KR100763542B1 (ko) * | 2006-10-30 | 2007-10-05 | 삼성전자주식회사 | 다중 채널 모오스 트랜지스터를 포함하는 반도체 장치의제조 방법 |
JP2008135711A (ja) * | 2006-11-01 | 2008-06-12 | Seiko Epson Corp | 半導体装置の製造方法、および半導体装置 |
JP2008153532A (ja) * | 2006-12-19 | 2008-07-03 | Seiko Epson Corp | 半導体装置の製造方法 |
JP4285536B2 (ja) * | 2006-12-19 | 2009-06-24 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US20080203484A1 (en) * | 2007-02-23 | 2008-08-28 | Infineon Technologies Ag | Field effect transistor arrangement and method of producing a field effect transistor arrangement |
-
2005
- 2005-01-21 FR FR0500674A patent/FR2881273B1/fr not_active Expired - Fee Related
-
2006
- 2006-01-19 US US11/335,857 patent/US7476574B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2881273A1 (fr) | 2006-07-28 |
US7476574B2 (en) | 2009-01-13 |
US20060189157A1 (en) | 2006-08-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20120928 |