FR2860340B1 - Collage indirect avec disparition de la couche de collage - Google Patents

Collage indirect avec disparition de la couche de collage

Info

Publication number
FR2860340B1
FR2860340B1 FR0311418A FR0311418A FR2860340B1 FR 2860340 B1 FR2860340 B1 FR 2860340B1 FR 0311418 A FR0311418 A FR 0311418A FR 0311418 A FR0311418 A FR 0311418A FR 2860340 B1 FR2860340 B1 FR 2860340B1
Authority
FR
France
Prior art keywords
bonding
disappearance
indirect
layer
bonding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0311418A
Other languages
English (en)
Other versions
FR2860340A1 (fr
Inventor
Nicolas Daval
Bruno Ghyselen
Cecile Aulnette
Olivier Rayssac
Ian Cayrefourcq
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0311418A priority Critical patent/FR2860340B1/fr
Priority to US10/753,173 priority patent/US7078353B2/en
Priority to PCT/IB2004/003324 priority patent/WO2005031852A1/fr
Priority to JP2006530756A priority patent/JP4739213B2/ja
Priority to EP04769613A priority patent/EP1668693A1/fr
Priority to CN200480028279A priority patent/CN100590838C/zh
Priority to KR1020067004222A priority patent/KR100834200B1/ko
Publication of FR2860340A1 publication Critical patent/FR2860340A1/fr
Application granted granted Critical
Publication of FR2860340B1 publication Critical patent/FR2860340B1/fr
Priority to JP2011005104A priority patent/JP2011109125A/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
FR0311418A 2003-09-30 2003-09-30 Collage indirect avec disparition de la couche de collage Expired - Fee Related FR2860340B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0311418A FR2860340B1 (fr) 2003-09-30 2003-09-30 Collage indirect avec disparition de la couche de collage
US10/753,173 US7078353B2 (en) 2003-09-30 2004-01-06 Indirect bonding with disappearance of bonding layer
JP2006530756A JP4739213B2 (ja) 2003-09-30 2004-09-30 ボンディング層が消滅する間接ボンディング
EP04769613A EP1668693A1 (fr) 2003-09-30 2004-09-30 Liaison indirecte avec disparition de la couche de liaison
PCT/IB2004/003324 WO2005031852A1 (fr) 2003-09-30 2004-09-30 Liaison indirecte avec disparition de la couche de liaison
CN200480028279A CN100590838C (zh) 2003-09-30 2004-09-30 键合层消失的间接键合
KR1020067004222A KR100834200B1 (ko) 2003-09-30 2004-09-30 전자공학, 공학 또는 광전자공학용 기판 제조방법, 및 제1웨이퍼와 제2웨이퍼의 반도체 재료 결합방법
JP2011005104A JP2011109125A (ja) 2003-09-30 2011-01-13 ボンディング層が消滅する間接ボンディング

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0311418A FR2860340B1 (fr) 2003-09-30 2003-09-30 Collage indirect avec disparition de la couche de collage

Publications (2)

Publication Number Publication Date
FR2860340A1 FR2860340A1 (fr) 2005-04-01
FR2860340B1 true FR2860340B1 (fr) 2006-01-27

Family

ID=34307262

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0311418A Expired - Fee Related FR2860340B1 (fr) 2003-09-30 2003-09-30 Collage indirect avec disparition de la couche de collage

Country Status (7)

Country Link
US (1) US7078353B2 (fr)
EP (1) EP1668693A1 (fr)
JP (2) JP4739213B2 (fr)
KR (1) KR100834200B1 (fr)
CN (1) CN100590838C (fr)
FR (1) FR2860340B1 (fr)
WO (1) WO2005031852A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176072B2 (en) * 2005-01-28 2007-02-13 Sharp Laboratories Of America, Inc Strained silicon devices transfer to glass for display applications
US8007675B1 (en) * 2005-07-11 2011-08-30 National Semiconductor Corporation System and method for controlling an etch process for a single crystal having a buried layer
DE102005061263B4 (de) * 2005-12-20 2007-10-11 Infineon Technologies Austria Ag Halbleiterwafersubstrat für Leistungshalbleiterbauelemente sowie Verfahren zur Herstellung desselben
FR2912550A1 (fr) * 2007-02-14 2008-08-15 Soitec Silicon On Insulator Procede de fabrication d'une structure ssoi.
FR2912841B1 (fr) * 2007-02-15 2009-05-22 Soitec Silicon On Insulator Procede de polissage d'heterostructures
KR100867924B1 (ko) * 2007-03-07 2008-11-10 삼성에스디아이 주식회사 도너기판, 그의 제조방법 및 유기전계발광소자
FR2932108B1 (fr) 2008-06-10 2019-07-05 Soitec Polissage de couches de germanium
FR2951869A1 (fr) * 2009-10-26 2011-04-29 Commissariat Energie Atomique Procede de realisation d'une structure a couche enterree par implantation et transfert
US8822817B2 (en) 2010-12-03 2014-09-02 The Boeing Company Direct wafer bonding
FR2972567B1 (fr) * 2011-03-09 2013-03-22 Soitec Silicon On Insulator Méthode de formation d'une structure de ge sur iii/v sur isolant
CN106548972B (zh) * 2015-09-18 2019-02-26 胡兵 一种将半导体衬底主体与其上功能层进行分离的方法
US10541172B2 (en) 2016-08-24 2020-01-21 International Business Machines Corporation Semiconductor device with reduced contact resistance
US9799618B1 (en) 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US10930793B2 (en) * 2017-04-21 2021-02-23 International Business Machines Corporation Bottom channel isolation in nanosheet transistors
CN109545766B (zh) * 2018-11-14 2020-08-21 长江存储科技有限责任公司 三维存储器及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
WO1999053539A1 (fr) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Systeme de couche d'arret d'attaque chimique au silicium et au germanium
JP3385972B2 (ja) * 1998-07-10 2003-03-10 信越半導体株式会社 貼り合わせウェーハの製造方法および貼り合わせウェーハ
US6602613B1 (en) * 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP2003520452A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション ひずみシリコン酸化金属半導体電界効果トランジスタ
JP3580358B2 (ja) 2000-06-23 2004-10-20 信越化学工業株式会社 熱伝導性シリコーン組成物及び半導体装置
DE60125952T2 (de) * 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US6724008B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
JP4628580B2 (ja) * 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法
JP2003031495A (ja) * 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
JP2003168789A (ja) * 2001-11-29 2003-06-13 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハの製造方法
US6746902B2 (en) * 2002-01-31 2004-06-08 Sharp Laboratories Of America, Inc. Method to form relaxed sige layer with high ge content
US6793731B2 (en) * 2002-03-13 2004-09-21 Sharp Laboratories Of America, Inc. Method for recrystallizing an amorphized silicon germanium film overlying silicon
US6841457B2 (en) * 2002-07-16 2005-01-11 International Business Machines Corporation Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate

Also Published As

Publication number Publication date
KR20060064061A (ko) 2006-06-12
FR2860340A1 (fr) 2005-04-01
US7078353B2 (en) 2006-07-18
US20050070078A1 (en) 2005-03-31
JP2007507874A (ja) 2007-03-29
JP2011109125A (ja) 2011-06-02
EP1668693A1 (fr) 2006-06-14
CN100590838C (zh) 2010-02-17
WO2005031852A1 (fr) 2005-04-07
CN1860604A (zh) 2006-11-08
JP4739213B2 (ja) 2011-08-03
KR100834200B1 (ko) 2008-05-30

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20140530