FR2773020B1 - Circuit de distribution d'horloge dans un circuit integre - Google Patents

Circuit de distribution d'horloge dans un circuit integre

Info

Publication number
FR2773020B1
FR2773020B1 FR9716723A FR9716723A FR2773020B1 FR 2773020 B1 FR2773020 B1 FR 2773020B1 FR 9716723 A FR9716723 A FR 9716723A FR 9716723 A FR9716723 A FR 9716723A FR 2773020 B1 FR2773020 B1 FR 2773020B1
Authority
FR
France
Prior art keywords
circuit
clock distribution
integrated circuit
integrated
distribution circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9716723A
Other languages
English (en)
Other versions
FR2773020A1 (fr
Inventor
Stephane Hanriat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9716723A priority Critical patent/FR2773020B1/fr
Priority to US09/216,898 priority patent/US6252449B1/en
Publication of FR2773020A1 publication Critical patent/FR2773020A1/fr
Application granted granted Critical
Publication of FR2773020B1 publication Critical patent/FR2773020B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
FR9716723A 1997-12-24 1997-12-24 Circuit de distribution d'horloge dans un circuit integre Expired - Fee Related FR2773020B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9716723A FR2773020B1 (fr) 1997-12-24 1997-12-24 Circuit de distribution d'horloge dans un circuit integre
US09/216,898 US6252449B1 (en) 1997-12-24 1998-12-21 Clock distribution circuit in an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9716723A FR2773020B1 (fr) 1997-12-24 1997-12-24 Circuit de distribution d'horloge dans un circuit integre

Publications (2)

Publication Number Publication Date
FR2773020A1 FR2773020A1 (fr) 1999-06-25
FR2773020B1 true FR2773020B1 (fr) 2000-03-10

Family

ID=9515314

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9716723A Expired - Fee Related FR2773020B1 (fr) 1997-12-24 1997-12-24 Circuit de distribution d'horloge dans un circuit integre

Country Status (2)

Country Link
US (1) US6252449B1 (fr)
FR (1) FR2773020B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586971B1 (en) 2001-12-18 2003-07-01 Hewlett-Packard Development Company, L.P. Adapting VLSI clocking to short term voltage transients
KR100440569B1 (ko) * 2001-12-20 2004-07-21 한국전자통신연구원 다중 밴드 모뎀의 클럭 분배장치
US6646472B1 (en) * 2002-05-28 2003-11-11 Sun Microsystems, Inc. Clock power reduction technique using multi-level voltage input clock driver
US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US7180353B2 (en) * 2005-02-03 2007-02-20 Mediatek Incorporation Apparatus and method for low power clock distribution
US7336115B2 (en) * 2005-02-09 2008-02-26 International Business Machines Corporation Redundancy in signal distribution trees
EP1835618A1 (fr) * 2006-03-16 2007-09-19 STMicroelectronics S.r.l. Réduction du temps d'exécution d'un transfert de données commandé en externe dans un dispositif intégré

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5580136A (en) * 1978-12-14 1980-06-17 Fujitsu Ltd Clock signal distribution system
JPS6477314A (en) * 1987-09-18 1989-03-23 Nec Corp Semiconductor circuit
JPH02228810A (ja) * 1989-03-02 1990-09-11 Nec Eng Ltd 逓倍回路
US5486774A (en) * 1991-11-26 1996-01-23 Nippon Telegraph And Telephone Corporation CMOS logic circuits having low and high-threshold voltage transistors
JPH06163827A (ja) * 1992-11-19 1994-06-10 Kawasaki Steel Corp 半導体集積回路
JPH07253825A (ja) * 1994-03-15 1995-10-03 Toshiba Corp 半導体集積回路のクロック信号分配方法およびこの方法に用いられる周波数逓倍器
US5670899A (en) * 1994-11-21 1997-09-23 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
US5705946A (en) * 1995-06-07 1998-01-06 Sgs-Thomson Microelectronics, Inc. Low power low voltage level shifter
US5519350A (en) * 1995-06-30 1996-05-21 At&T Corp. Circuitry for delivering a signal to different load elements located in an electronic system
US5669684A (en) * 1995-12-07 1997-09-23 Agan; Tom A. Logic level shifter with power on control
JP2959482B2 (ja) * 1996-08-19 1999-10-06 日本電気株式会社 大規模集積回路
KR100197998B1 (ko) * 1996-10-22 1999-06-15 김영환 반도체 장치의 저소비 전력 입력 버퍼

Also Published As

Publication number Publication date
FR2773020A1 (fr) 1999-06-25
US6252449B1 (en) 2001-06-26

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Legal Events

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CD Change of name or company name
ST Notification of lapse

Effective date: 20070831