GB2321118B - Development of integrated circuits - Google Patents
Development of integrated circuitsInfo
- Publication number
- GB2321118B GB2321118B GB9700599A GB9700599A GB2321118B GB 2321118 B GB2321118 B GB 2321118B GB 9700599 A GB9700599 A GB 9700599A GB 9700599 A GB9700599 A GB 9700599A GB 2321118 B GB2321118 B GB 2321118B
- Authority
- GB
- United Kingdom
- Prior art keywords
- development
- integrated circuits
- circuits
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9700599A GB2321118B (en) | 1997-01-14 | 1997-01-14 | Development of integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9700599A GB2321118B (en) | 1997-01-14 | 1997-01-14 | Development of integrated circuits |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9700599D0 GB9700599D0 (en) | 1997-03-05 |
GB2321118A GB2321118A (en) | 1998-07-15 |
GB2321118B true GB2321118B (en) | 2002-03-27 |
Family
ID=10805905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9700599A Expired - Fee Related GB2321118B (en) | 1997-01-14 | 1997-01-14 | Development of integrated circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2321118B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2371640B (en) | 2001-01-26 | 2004-09-01 | Advanced Risc Mach Ltd | Validating integrated circuits |
US7526745B2 (en) | 2004-12-08 | 2009-04-28 | Telefonaktiebolaget L M Ericsson (Publ) | Method for specification and integration of reusable IP constraints |
DE112005003449A5 (en) * | 2005-03-04 | 2008-01-10 | Qimonda Ag | Test method and method for a semiconductor circuit composed of subcircuits |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0296812A2 (en) * | 1987-06-22 | 1988-12-28 | Cadence Design Systems, Inc. | Block diagram simulator |
WO1989003087A2 (en) * | 1987-10-01 | 1989-04-06 | International Standard Electric Corporation | System integrated fault-tree analysis methods (siftan) |
US4870575A (en) * | 1987-10-01 | 1989-09-26 | Itt Corporation | System integrated fault-tree analysis methods (SIFTAN) |
EP0442277A2 (en) * | 1990-02-16 | 1991-08-21 | International Business Machines Corporation | A logic simulation using a hardware accelerator together with an automated error event isolation and trace facility |
US5437037A (en) * | 1992-06-05 | 1995-07-25 | Mega Chips Corporation | Simulation using compiled function description language |
US5574893A (en) * | 1992-10-29 | 1996-11-12 | Altera Corporation | Computer logic simulation with dynamic modeling |
-
1997
- 1997-01-14 GB GB9700599A patent/GB2321118B/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0296812A2 (en) * | 1987-06-22 | 1988-12-28 | Cadence Design Systems, Inc. | Block diagram simulator |
WO1989003087A2 (en) * | 1987-10-01 | 1989-04-06 | International Standard Electric Corporation | System integrated fault-tree analysis methods (siftan) |
US4870575A (en) * | 1987-10-01 | 1989-09-26 | Itt Corporation | System integrated fault-tree analysis methods (SIFTAN) |
EP0442277A2 (en) * | 1990-02-16 | 1991-08-21 | International Business Machines Corporation | A logic simulation using a hardware accelerator together with an automated error event isolation and trace facility |
US5437037A (en) * | 1992-06-05 | 1995-07-25 | Mega Chips Corporation | Simulation using compiled function description language |
US5574893A (en) * | 1992-10-29 | 1996-11-12 | Altera Corporation | Computer logic simulation with dynamic modeling |
Also Published As
Publication number | Publication date |
---|---|
GB9700599D0 (en) | 1997-03-05 |
GB2321118A (en) | 1998-07-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |