FR2426937A1 - Systeme de traitement de donnees - Google Patents
Systeme de traitement de donneesInfo
- Publication number
- FR2426937A1 FR2426937A1 FR7913019A FR7913019A FR2426937A1 FR 2426937 A1 FR2426937 A1 FR 2426937A1 FR 7913019 A FR7913019 A FR 7913019A FR 7913019 A FR7913019 A FR 7913019A FR 2426937 A1 FR2426937 A1 FR 2426937A1
- Authority
- FR
- France
- Prior art keywords
- subsystem
- memory
- adapter
- originating
- identification data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Memory System (AREA)
- Small-Scale Networks (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Abstract
Un système de traitement de données comprend un premier et un second bus de communication 12,14, un sous-système mémoire 20 étant connecté à un accès adréssable du second bus 14. Le sous-système origine 24 fournit un message de demande mémoire qui est transmis au bus 12 par l'intermédiaire d'un premier et d'un second adaptateurs de communication mémoire. Le second adaptateur 28 stocke des données d'identification d'origine identifiant le sous-système origine 24 et substitue d'autres données d'identification d'origine identifiant le second adaptateur 28. Le message de réponse mémoire émis par le sous-système mémoire 20 est ensuite reçu par le second adaptateur 28 qui modifie le message pour qu'il contienne, comme informations de destination, les données d'identification initiales identifiant le sous-système origine 24.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/908,183 US4205373A (en) | 1978-05-22 | 1978-05-22 | System and method for accessing memory connected to different bus and requesting subsystem |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2426937A1 true FR2426937A1 (fr) | 1979-12-21 |
FR2426937B1 FR2426937B1 (fr) | 1986-06-13 |
Family
ID=25425331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7913019A Expired FR2426937B1 (fr) | 1978-05-22 | 1979-05-22 | Systeme de traitement de donnees |
Country Status (5)
Country | Link |
---|---|
US (1) | US4205373A (fr) |
JP (1) | JPS54152928A (fr) |
DE (1) | DE2920490C2 (fr) |
FR (1) | FR2426937B1 (fr) |
GB (1) | GB2021824B (fr) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527237A (en) * | 1979-10-11 | 1985-07-02 | Nanodata Computer Corporation | Data processing system |
US5146572A (en) * | 1980-11-17 | 1992-09-08 | International Business Machines Corporation | Multiple data format interface |
US4520452A (en) * | 1982-03-16 | 1985-05-28 | Burroughs Corporation | Memory selection in a multiple line adapter organization |
CA1184312A (fr) * | 1982-03-16 | 1985-03-19 | Richard A. Loskorn | Selection de memoires dans une organisation a adaptateurs de ligne multiples |
US4667305A (en) * | 1982-06-30 | 1987-05-19 | International Business Machines Corporation | Circuits for accessing a variable width data bus with a variable width data field |
US4751727A (en) * | 1982-09-30 | 1988-06-14 | American Telephone And Telegraph Company, At&T Bell Laboratories | Multiprocessor computing system featuring shared global control |
US4713834A (en) * | 1982-09-30 | 1987-12-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Multiprocessor computing system featuring shared global control |
US4626634A (en) * | 1982-09-30 | 1986-12-02 | At&T Bell Laboratories | Multiprocessor computing system featuring shared global control |
US4663729A (en) * | 1984-06-01 | 1987-05-05 | International Business Machines Corp. | Display architecture having variable data width |
US4766564A (en) * | 1984-08-13 | 1988-08-23 | International Business Machines Corporation | Dual putaway/bypass busses for multiple arithmetic units |
CA1239227A (fr) * | 1984-10-17 | 1988-07-12 | Randy D. Pfeifer | Methode et dispositif d'ordonnancement des operations dans un systeme multiprocesseur |
US4768145A (en) * | 1984-11-28 | 1988-08-30 | Hewlett-Packard Company | Bus system |
US4787029A (en) * | 1986-09-29 | 1988-11-22 | Gte Communication Systems Corporation | Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor |
US4890254A (en) * | 1987-03-11 | 1989-12-26 | Aristacom International, Inc. | Clock disabling circuit |
US4958342A (en) * | 1987-03-11 | 1990-09-18 | Aristacom International, Inc. | Adaptive digital network interface |
US4882727A (en) * | 1987-03-11 | 1989-11-21 | Aristacom International, Inc. | Adaptive digital network interface |
US5029074A (en) * | 1987-06-29 | 1991-07-02 | Digital Equipment Corporation | Bus adapter unit for digital processing system |
US4935894A (en) * | 1987-08-31 | 1990-06-19 | Motorola, Inc. | Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information |
GB2211326B (en) * | 1987-10-16 | 1991-12-11 | Hitachi Ltd | Address bus control apparatus |
US5093807A (en) * | 1987-12-23 | 1992-03-03 | Texas Instruments Incorporated | Video frame storage system |
US5587962A (en) * | 1987-12-23 | 1996-12-24 | Texas Instruments Incorporated | Memory circuit accommodating both serial and random access including an alternate address buffer register |
US5081576A (en) * | 1988-03-24 | 1992-01-14 | Encore Computer U.S., Inc. | Advance polling bus arbiter for use in multiple bus system |
US5138703A (en) * | 1988-03-31 | 1992-08-11 | Kabushiki Kaisha Toshiba | Method of and apparatus for expanding system bus |
US4987529A (en) * | 1988-08-11 | 1991-01-22 | Ast Research, Inc. | Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters |
EP0357075A3 (fr) * | 1988-09-02 | 1991-12-11 | Fujitsu Limited | Dispositif de commande de données et système utilisant le dispositif |
US5191657A (en) * | 1989-11-09 | 1993-03-02 | Ast Research, Inc. | Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus |
US5243703A (en) * | 1990-04-18 | 1993-09-07 | Rambus, Inc. | Apparatus for synchronously generating clock signals in a data processing system |
US6751696B2 (en) * | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
EP0994420B1 (fr) * | 1990-04-18 | 2006-01-04 | Rambus Inc. | Appareil semiconducteur DRAM |
US5369748A (en) * | 1991-08-23 | 1994-11-29 | Nexgen Microsystems | Bus arbitration in a dual-bus architecture where one bus has relatively high latency |
US5341495A (en) * | 1991-10-04 | 1994-08-23 | Bull Hn Information Systems, Inc. | Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols |
JP3524110B2 (ja) * | 1992-11-06 | 2004-05-10 | 株式会社ルネサステクノロジ | マイクロコンピュータシステム |
US5649127A (en) * | 1994-05-04 | 1997-07-15 | Samsung Semiconductor, Inc. | Method and apparatus for packing digital data |
US5905961A (en) * | 1997-02-05 | 1999-05-18 | Motorola, Inc. | Method and apparatus for managing remote unit increased power transmission during location |
US6185651B1 (en) | 1997-11-05 | 2001-02-06 | Compaq Computer Corp | SCSI bus extender utilizing tagged queuing in a multi-initiator environment |
KR100261218B1 (ko) * | 1997-12-08 | 2000-07-01 | 윤종용 | 반도체 메모리 장치의 핀 어사인먼트 방법 및 패킷 단위의 신호를 입력으로 하는 반도체 메모리장치 |
US6141710A (en) * | 1998-12-15 | 2000-10-31 | Daimlerchrysler Corporation | Interfacing vehicle data bus to intelligent transportation system (ITS) data bus via a gateway module |
US6658519B1 (en) * | 2000-07-28 | 2003-12-02 | International Business Machines Corporation | Bus bridge with embedded input/output (I/O) and transaction tracing capabilities |
US7013355B2 (en) * | 2003-01-09 | 2006-03-14 | Micrel, Incorporated | Device and method for improved serial bus transaction using incremental address decode |
US20070027485A1 (en) * | 2005-07-29 | 2007-02-01 | Kallmyer Todd A | Implantable medical device bus system and method |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3932841A (en) * | 1973-10-26 | 1976-01-13 | Raytheon Company | Bus controller for digital computer system |
US3940743A (en) * | 1973-11-05 | 1976-02-24 | Digital Equipment Corporation | Interconnecting unit for independently operable data processing systems |
US3890471A (en) * | 1973-12-17 | 1975-06-17 | Bell Telephone Labor Inc | Loop data transmission arrangement employing an interloop communication terminal |
US4041472A (en) * | 1976-04-29 | 1977-08-09 | Ncr Corporation | Data processing internal communications system having plural time-shared intercommunication buses and inter-bus communication means |
-
1978
- 1978-05-22 US US05/908,183 patent/US4205373A/en not_active Expired - Lifetime
-
1979
- 1979-05-18 GB GB7917367A patent/GB2021824B/en not_active Expired
- 1979-05-21 DE DE2920490A patent/DE2920490C2/de not_active Expired
- 1979-05-21 JP JP6162379A patent/JPS54152928A/ja active Granted
- 1979-05-22 FR FR7913019A patent/FR2426937B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS54152928A (en) | 1979-12-01 |
GB2021824A (en) | 1979-12-05 |
GB2021824B (en) | 1982-02-10 |
DE2920490A1 (de) | 1979-11-29 |
JPS6250862B2 (fr) | 1987-10-27 |
US4205373A (en) | 1980-05-27 |
FR2426937B1 (fr) | 1986-06-13 |
DE2920490C2 (de) | 1983-05-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |