FR2420168A1 - Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees - Google Patents
Dispositif de pre-traitement d'instructions dans un systeme de traitement de donneesInfo
- Publication number
- FR2420168A1 FR2420168A1 FR7902412A FR7902412A FR2420168A1 FR 2420168 A1 FR2420168 A1 FR 2420168A1 FR 7902412 A FR7902412 A FR 7902412A FR 7902412 A FR7902412 A FR 7902412A FR 2420168 A1 FR2420168 A1 FR 2420168A1
- Authority
- FR
- France
- Prior art keywords
- instruction
- fields
- instructions
- data processing
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007781 pre-processing Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
Circuit logique permettant le pré-décodage et la mise en file d'attente d'instructions. Les circuits peuvent être commandés par des instructions de chargement de registres indentifiant un, deux ou plusieurs registres généraux. Deux champs d'identification de registres sont prévus pour chaque instruction pré-décodée introduite dans une file d'instructions. Des circuits de comparaison comparent ces champs et les champs d'adressage de registres dans l'instruction en cours de décodage. L'invention permet d'améliorer les performances des dispositifs de pré-décodage d'instructions.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US88709378A | 1978-03-16 | 1978-03-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2420168A1 true FR2420168A1 (fr) | 1979-10-12 |
FR2420168B1 FR2420168B1 (fr) | 1986-09-26 |
Family
ID=25390443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7902412A Expired FR2420168B1 (fr) | 1978-03-16 | 1979-01-25 | Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS54127649A (fr) |
DE (1) | DE2906685A1 (fr) |
FR (1) | FR2420168B1 (fr) |
GB (1) | GB2016753A (fr) |
IT (1) | IT1166667B (fr) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2561429B1 (fr) * | 1984-03-13 | 1986-09-19 | Trt Telecom Radio Electr | Dispositif d'adressage pour fournir a une memoire des codes d'adresse |
FI86484C (fi) * | 1984-04-27 | 1992-08-25 | Honeywell Inf Systems | Styrorgan i en digital datamaskin. |
DE3650578T2 (de) * | 1985-06-17 | 1997-03-06 | Nippon Electric Co | Informationsverarbeitungssystem mit einer Steuerschaltung zum Abwarten einer Registererneuerung und einem Aufnahmemittel des zu erneuernden Registers |
JPS6227829A (ja) * | 1985-07-30 | 1987-02-05 | Fujitsu Ltd | 多重ロード命令制御装置 |
US5167026A (en) * | 1989-02-03 | 1992-11-24 | Digital Equipment Corporation | Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers |
US5142631A (en) * | 1989-02-03 | 1992-08-25 | Digital Equipment Corporation | System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register |
US5450555A (en) * | 1990-06-29 | 1995-09-12 | Digital Equipment Corporation | Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions |
US5471591A (en) * | 1990-06-29 | 1995-11-28 | Digital Equipment Corporation | Combined write-operand queue and read-after-write dependency scoreboard |
US5432918A (en) * | 1990-06-29 | 1995-07-11 | Digital Equipment Corporation | Method and apparatus for ordering read and write operations using conflict bits in a write queue |
DE69130138T2 (de) * | 1990-06-29 | 1999-05-06 | Digital Equipment Corp., Maynard, Mass. | Sprungvorhersageeinheit für hochleistungsfähigen Prozessor |
US11457671B2 (en) | 2019-12-20 | 2022-10-04 | Maddox Holdings Inc. | Maternity undergarment for gentle support and shape enhancement |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3477063A (en) * | 1967-10-26 | 1969-11-04 | Ibm | Controller for data processing system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5320180B2 (fr) * | 1972-05-09 | 1978-06-24 | ||
JPS5240946B2 (fr) * | 1972-09-06 | 1977-10-15 | ||
JPS5041442A (fr) * | 1973-08-16 | 1975-04-15 | ||
JPS5318931A (en) * | 1976-08-06 | 1978-02-21 | Hitachi Ltd | Information processor |
-
1979
- 1979-01-25 FR FR7902412A patent/FR2420168B1/fr not_active Expired
- 1979-02-05 JP JP1150679A patent/JPS54127649A/ja active Granted
- 1979-02-21 DE DE19792906685 patent/DE2906685A1/de active Granted
- 1979-02-27 IT IT20567/79A patent/IT1166667B/it active
- 1979-03-15 GB GB7909169A patent/GB2016753A/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3477063A (en) * | 1967-10-26 | 1969-11-04 | Ibm | Controller for data processing system |
Also Published As
Publication number | Publication date |
---|---|
GB2016753B (fr) | |
JPS54127649A (en) | 1979-10-03 |
GB2016753A (en) | 1979-09-26 |
JPS6112289B2 (fr) | 1986-04-07 |
IT7920567A0 (it) | 1979-02-27 |
FR2420168B1 (fr) | 1986-09-26 |
DE2906685C2 (fr) | 1988-04-14 |
IT1166667B (it) | 1987-05-06 |
DE2906685A1 (de) | 1979-09-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2363948A1 (fr) | Procede et dispositif pour le codage d'images avec redondance reduite | |
FR2420168A1 (fr) | Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees | |
KR910012913A (ko) | 명령태그(tag)장치를 구비한 테이터처리시스팀 | |
DE68924380D1 (de) | Vernichtung von Pipelineblasen in einem Rechnersystem. | |
KR930002961A (ko) | 멀티프로세서 파이프라인에 걸리는 프로세싱 로드를 동적으로 균형시키기 위해 높은 레벨의 명령신호를 프로세싱하는 장치 및 방법 | |
MY100954A (en) | Data processing system with cpu register to register data transfers overlapped with data transfer to and from main storage. | |
BE745547A (fr) | Dispositif pour commander l'echelonnement sequentiel d'instructions dans un systeme de traitement d'informations. | |
KR910005154A (ko) | 파이프라인된 기록버퍼 레지스터 | |
JPS6462764A (en) | Vector computer | |
WO1997001814A3 (fr) | Systeme de traitement d'interruptions | |
KR900003743A (ko) | 명령파이프라인방식의 마이크로프로세서 | |
KR910008565A (ko) | 분기 제어 회로 | |
EP0814411A3 (fr) | Dispositif de traitement de données vectorielles | |
CA2053740A1 (fr) | Procede pour la ratification de codes secrets pour cartes a memoire | |
FR2443723A1 (fr) | Dispositif de reduction du temps d'acces aux informations contenues dans une memoire d'un systeme de traitement de l'information | |
DE69430973D1 (de) | Informationsverarbeitungssystem mit einem Cachespeicher und Vorrichtung zur Datenvorausholung | |
TW355770B (en) | Program execution method and device using the same | |
OA00813A (fr) | Dispositif pour le traitement d'une information initiale suivant un ordre conditionnel prédéterminé. | |
WO2002044894A3 (fr) | Procede et dispositif destines a la representation d'instructions machine a taille variable | |
KR880003241A (ko) | 데이타 처리 시스템 | |
FR2440049A1 (fr) | Commande de dispositif d'affichage pour positions d'operatrices | |
GB1081986A (en) | Data processing apparatus | |
JPS58101360A (ja) | デ−タ処理装置 | |
FR2407519A1 (fr) | Unite de traitement centrale pouvant executer des instructions de longueur variable | |
JPS61289428A (ja) | マイクロプロセツサ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |