FR2313712A1 - Dispositif logique de detection de sommes - Google Patents

Dispositif logique de detection de sommes

Info

Publication number
FR2313712A1
FR2313712A1 FR7610902A FR7610902A FR2313712A1 FR 2313712 A1 FR2313712 A1 FR 2313712A1 FR 7610902 A FR7610902 A FR 7610902A FR 7610902 A FR7610902 A FR 7610902A FR 2313712 A1 FR2313712 A1 FR 2313712A1
Authority
FR
France
Prior art keywords
logic device
detection logic
sum detection
sum
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7610902A
Other languages
English (en)
Other versions
FR2313712B1 (fr
Inventor
Arnold Weinberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2313712A1 publication Critical patent/FR2313712A1/fr
Application granted granted Critical
Publication of FR2313712B1 publication Critical patent/FR2313712B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
FR7610902A 1975-06-02 1976-04-08 Dispositif logique de detection de sommes Granted FR2313712A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/583,023 US3983382A (en) 1975-06-02 1975-06-02 Adder with fast detection of sum equal to zeroes or radix minus one

Publications (2)

Publication Number Publication Date
FR2313712A1 true FR2313712A1 (fr) 1976-12-31
FR2313712B1 FR2313712B1 (fr) 1979-06-01

Family

ID=24331369

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7610902A Granted FR2313712A1 (fr) 1975-06-02 1976-04-08 Dispositif logique de detection de sommes

Country Status (5)

Country Link
US (1) US3983382A (fr)
JP (1) JPS51147932A (fr)
DE (1) DE2623986A1 (fr)
FR (1) FR2313712A1 (fr)
GB (1) GB1531919A (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504924A (en) * 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates
JPS59121539A (ja) * 1982-12-28 1984-07-13 Fujitsu Ltd 条件コ−ド決定回路
US4630192A (en) * 1983-05-18 1986-12-16 International Business Machines Corporation Apparatus for executing an instruction and for simultaneously generating and storing related information
JPS59226944A (ja) * 1983-06-09 1984-12-20 Fujitsu Ltd 浮動小数点デ−タ加減算方式
US4638450A (en) * 1983-09-30 1987-01-20 Honeywell Information Systems Inc. Equal nine apparatus for supporting absolute value subtracts on decimal operands of unequal length
US4815019A (en) * 1987-02-26 1989-03-21 Texas Instruments Incorporated Fast ALU equals zero circuit
US4947359A (en) * 1988-02-17 1990-08-07 International Business Machines Corporation Apparatus and method for prediction of zero arithmetic/logic results
US4924422A (en) * 1988-02-17 1990-05-08 International Business Machines Corporation Method and apparatus for modified carry-save determination of arithmetic/logic zero results
JPH01277931A (ja) * 1988-04-29 1989-11-08 Nec Ic Microcomput Syst Ltd 零検出回路
EP0478745A4 (en) * 1990-04-04 1993-09-01 International Business Machines Corporation High performance interlock collapsing scism alu apparatus
US5359718A (en) * 1991-03-29 1994-10-25 International Business Machines Corporation Early scalable instruction set machine alu status prediction apparatus
US5258942A (en) * 1992-03-20 1993-11-02 Vlsi Technology, Inc. Balanced two-level delay propagation all one detector compiler
US5581496A (en) * 1992-07-20 1996-12-03 Industrial Technology Research Institute Zero-flag generator for adder
US5270955A (en) * 1992-07-31 1993-12-14 Texas Instruments Incorporated Method of detecting arithmetic or logical computation result
US5469377A (en) * 1992-08-18 1995-11-21 Nec Corporation Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1
US5367477A (en) * 1993-11-29 1994-11-22 Motorola, Inc. Method and apparatus for performing parallel zero detection in a data processing system
JPH07191831A (ja) * 1993-12-27 1995-07-28 Fujitsu Ltd 演算装置
GB9404377D0 (en) * 1994-03-07 1994-04-20 Texas Instruments Ltd Improvements in or relating to a comparator scheme
US5586069A (en) * 1994-09-30 1996-12-17 Vlsi Technology, Inc. Arithmetic logic unit with zero sum prediction
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
US5968397A (en) * 1997-06-06 1999-10-19 Amana Company, L.P. Apparatus for cooling a quartz halogen lamp with heat conducting convector secured to the lamp terminal or socket
GB2342729B (en) * 1998-06-10 2003-03-12 Lsi Logic Corp Zero detection in digital processing
US6546411B1 (en) * 1999-12-03 2003-04-08 International Business Machines Corporation High-speed radix 100 parallel adder
CN106484361A (zh) * 2015-08-24 2017-03-08 韩青松 十进制数字加法器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1145676A (en) * 1966-09-28 1969-03-19 Nippon Electric Co High speed adder circuit
US3697735A (en) * 1969-07-22 1972-10-10 Burroughs Corp High-speed parallel binary adder
US3629565A (en) * 1970-02-13 1971-12-21 Ibm Improved decimal adder for directly implementing bcd addition utilizing logic circuitry

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NEANT *

Also Published As

Publication number Publication date
DE2623986A1 (de) 1976-12-16
US3983382A (en) 1976-09-28
JPS5747448B2 (fr) 1982-10-09
FR2313712B1 (fr) 1979-06-01
JPS51147932A (en) 1976-12-18
GB1531919A (en) 1978-11-15

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Legal Events

Date Code Title Description
ST Notification of lapse