FR2312856A1 - EDGE ENGRAVING PROCESS AND STRUCTURE TO PRODUCE NARROW OPENINGS ENDING THE SURFACE OF MATERIALS - Google Patents
EDGE ENGRAVING PROCESS AND STRUCTURE TO PRODUCE NARROW OPENINGS ENDING THE SURFACE OF MATERIALSInfo
- Publication number
- FR2312856A1 FR2312856A1 FR7615774A FR7615774A FR2312856A1 FR 2312856 A1 FR2312856 A1 FR 2312856A1 FR 7615774 A FR7615774 A FR 7615774A FR 7615774 A FR7615774 A FR 7615774A FR 2312856 A1 FR2312856 A1 FR 2312856A1
- Authority
- FR
- France
- Prior art keywords
- materials
- engraving process
- narrow openings
- produce narrow
- edge engraving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/7685—Three-Phase CCD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823406—Combination of charge coupled devices, i.e. CCD, or BBD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/76841—Two-Phase CCD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58138975A | 1975-05-27 | 1975-05-27 | |
US05/619,735 US4063992A (en) | 1975-05-27 | 1975-10-06 | Edge etch method for producing narrow openings to the surface of materials |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2312856A1 true FR2312856A1 (en) | 1976-12-24 |
FR2312856B1 FR2312856B1 (en) | 1982-11-05 |
Family
ID=27078310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7615774A Granted FR2312856A1 (en) | 1975-05-27 | 1976-05-25 | EDGE ENGRAVING PROCESS AND STRUCTURE TO PRODUCE NARROW OPENINGS ENDING THE SURFACE OF MATERIALS |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS51145274A (en) |
CA (1) | CA1076934A (en) |
DE (1) | DE2622790A1 (en) |
FR (1) | FR2312856A1 (en) |
GB (1) | GB1543845A (en) |
NL (1) | NL7605549A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2454698A1 (en) * | 1979-04-20 | 1980-11-14 | Radiotechnique Compelec | METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD |
FR2487125A1 (en) * | 1980-07-21 | 1982-01-22 | Data General Corp | PROCESS FOR FORMING NARROW AREAS IN INTEGRATED CIRCUITS, ESPECIALLY FOR THE FORMATION OF GRIDS, THE ISOLATION OF COMPONENTS, THE FORMATION OF DOPED REGIONS AND THE MANUFACTURE OF TRANSISTORS |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS544570A (en) * | 1977-06-13 | 1979-01-13 | Nec Corp | Production of semiconductor devices |
JPS5533064A (en) * | 1978-08-29 | 1980-03-08 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of manufacturing semiconductor device |
DE2939488A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING INTEGRATED SEMICONDUCTOR CIRCUITS, IN PARTICULAR CCD CIRCUITS, WITH SELF-ADJUSTED, NON-OVERLAPPING POLY-SILICON ELECTRODES |
DE2939456A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING INTEGRATED SEMICONDUCTOR CIRCUITS, IN PARTICULAR CCD CIRCUITS, WITH SELF-ADJUSTED, NON-OVERLAPPING POLY-SILICON ELECTRODES |
JPS581878A (en) * | 1981-06-26 | 1983-01-07 | Fujitsu Ltd | Production of bubble memory device |
US5126811A (en) * | 1990-01-29 | 1992-06-30 | Mitsubishi Denki Kabushiki Kaisha | Charge transfer device with electrode structure of high transfer efficiency |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2018027A1 (en) * | 1969-04-15 | 1970-10-22 | Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) | Process for making extremely fine openings |
FR2305022A1 (en) * | 1975-03-21 | 1976-10-15 | Western Electric Co | Field effect transistors prodn - with short channel between source and drain |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4874178A (en) * | 1971-12-29 | 1973-10-05 |
-
1976
- 1976-05-04 GB GB1818676A patent/GB1543845A/en not_active Expired
- 1976-05-21 DE DE19762622790 patent/DE2622790A1/en not_active Withdrawn
- 1976-05-24 NL NL7605549A patent/NL7605549A/en not_active Application Discontinuation
- 1976-05-25 FR FR7615774A patent/FR2312856A1/en active Granted
- 1976-05-26 CA CA253,422A patent/CA1076934A/en not_active Expired
- 1976-05-27 JP JP6070876A patent/JPS51145274A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2018027A1 (en) * | 1969-04-15 | 1970-10-22 | Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) | Process for making extremely fine openings |
FR2305022A1 (en) * | 1975-03-21 | 1976-10-15 | Western Electric Co | Field effect transistors prodn - with short channel between source and drain |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2454698A1 (en) * | 1979-04-20 | 1980-11-14 | Radiotechnique Compelec | METHOD FOR PRODUCING INTEGRATED CIRCUITS USING A MULTILAYER MASK AND DEVICES OBTAINED BY THIS METHOD |
FR2487125A1 (en) * | 1980-07-21 | 1982-01-22 | Data General Corp | PROCESS FOR FORMING NARROW AREAS IN INTEGRATED CIRCUITS, ESPECIALLY FOR THE FORMATION OF GRIDS, THE ISOLATION OF COMPONENTS, THE FORMATION OF DOPED REGIONS AND THE MANUFACTURE OF TRANSISTORS |
Also Published As
Publication number | Publication date |
---|---|
CA1076934A (en) | 1980-05-06 |
DE2622790A1 (en) | 1976-12-09 |
AU1437576A (en) | 1977-12-01 |
GB1543845A (en) | 1979-04-11 |
JPS51145274A (en) | 1976-12-14 |
JPS5711505B2 (en) | 1982-03-04 |
FR2312856B1 (en) | 1982-11-05 |
NL7605549A (en) | 1976-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ZA763840B (en) | Process for the manufacture of planographic printing form | |
JPS542403A (en) | Production of size treated paper sheet | |
JPS51143409A (en) | Method of making lithographic press plate | |
RO78125A (en) | PROCESS FOR THE PREPARATION OF SULFONYL-BENZIMIDAZOLE PROCESS FOR THE PREPARATION OF SULFONYLBENZIMIDAZOLES S WITH ANTIVIROTIC ACTION | |
JPS51136745A (en) | Multiilevel embossing of sheet material | |
FR2312856A1 (en) | EDGE ENGRAVING PROCESS AND STRUCTURE TO PRODUCE NARROW OPENINGS ENDING THE SURFACE OF MATERIALS | |
FR2325761A1 (en) | NEW DYING OR PRINTING PROCESS | |
NZ187218A (en) | Production of planographic printing plate | |
JPS5268267A (en) | Process for manufacture of sheet having embossed pattern | |
JPS5246901A (en) | Method of producing printing plate material | |
JPS51134204A (en) | Method of making lithographic press plate | |
JPS529504A (en) | Inverted halfftone gravure plate making method | |
FR2334783A2 (en) | FIBROUS MATERIAL PRINTING PROCESS | |
JPS5241014A (en) | Method of embossed transferred printing | |
JPS5240611A (en) | Production of art and engraving paper with pattern | |
IT1062947B (en) | APPARATUS TO APPLY MAGNETIC INK DROPS TO A REGISTRATION SURFACE | |
JPS54126226A (en) | Production of inorganic plate having surface patterned by multiilevel impression | |
ATA227577A (en) | MATERIAL FOR THE PRODUCTION OF SURFACE COATINGS ON WALLS | |
JPS5317404A (en) | Method of making printing form for inverted halfftone gravure plate making | |
ATA538177A (en) | PLATE PRESS FOR THE PRODUCTION OF LAMINATES AND SIMILAR SHAPED BODIES | |
JPS5273972A (en) | Process for manufacture of sheet having embossed pattern | |
JPS522607A (en) | Method of decorating surface of sheet material | |
JPS529502A (en) | Method of making printing plate | |
JPS53100005A (en) | Method of engraving printing plate | |
BE849360A (en) | PROCESS FOR PRODUCING BLACK SHEET WITH LUBRICATING SURFACE |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |