FR2007604A1 - - Google Patents

Info

Publication number
FR2007604A1
FR2007604A1 FR6913913A FR6913913A FR2007604A1 FR 2007604 A1 FR2007604 A1 FR 2007604A1 FR 6913913 A FR6913913 A FR 6913913A FR 6913913 A FR6913913 A FR 6913913A FR 2007604 A1 FR2007604 A1 FR 2007604A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR6913913A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of FR2007604A1 publication Critical patent/FR2007604A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607Interleaved addressing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
FR6913913A 1968-05-01 1969-04-30 Withdrawn FR2007604A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US72586268A 1968-05-01 1968-05-01

Publications (1)

Publication Number Publication Date
FR2007604A1 true FR2007604A1 (fr) 1970-01-09

Family

ID=24916265

Family Applications (1)

Application Number Title Priority Date Filing Date
FR6913913A Withdrawn FR2007604A1 (fr) 1968-05-01 1969-04-30

Country Status (5)

Country Link
US (1) US3546680A (fr)
DE (1) DE1922304A1 (fr)
FR (1) FR2007604A1 (fr)
GB (1) GB1264167A (fr)
NL (1) NL6906299A (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924241A (en) * 1971-03-15 1975-12-02 Burroughs Corp Memory cycle initiation in response to the presence of the memory address
US3919695A (en) * 1973-12-26 1975-11-11 Ibm Asynchronous clocking apparatus
US4285039A (en) * 1978-03-28 1981-08-18 Motorola, Inc. Memory array selection mechanism
US4321667A (en) * 1979-10-31 1982-03-23 International Business Machines Corp. Add-on programs with code verification and control
US4371929A (en) * 1980-05-05 1983-02-01 Ibm Corporation Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory
JPS5790740A (en) * 1980-11-26 1982-06-05 Nec Corp Information transfer device
US5448519A (en) * 1984-10-05 1995-09-05 Hitachi, Ltd. Memory device
KR910000365B1 (ko) * 1984-10-05 1991-01-24 가부시기가이샤 히다찌세이사꾸쇼 기억회로
US5450342A (en) * 1984-10-05 1995-09-12 Hitachi, Ltd. Memory device
DE3436679A1 (de) * 1984-10-05 1986-04-10 Franz 8922 Peiting Henke Hydropneumatische antriebsvorrichtung
US5923591A (en) * 1985-09-24 1999-07-13 Hitachi, Ltd. Memory circuit
US6028795A (en) 1985-09-24 2000-02-22 Hitachi, Ltd. One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation
US5265234A (en) * 1985-05-20 1993-11-23 Hitachi, Ltd. Integrated memory circuit and function unit with selective storage of logic functions
JPS62258207A (ja) * 1986-04-30 1987-11-10 Sumio Sugawara 複合流体圧シリンダ装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3242467A (en) * 1960-06-07 1966-03-22 Ibm Temporary storage register
US3323109A (en) * 1963-12-30 1967-05-30 North American Aviation Inc Multiple computer-multiple memory system
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
US3395392A (en) * 1965-10-22 1968-07-30 Ibm Expanded memory system
US3440616A (en) * 1966-05-16 1969-04-22 Gen Electric Data storage access control apparatus for a multicomputer system
US3436734A (en) * 1966-06-21 1969-04-01 Ibm Error correcting and repairable data processing storage system

Also Published As

Publication number Publication date
GB1264167A (fr) 1972-02-16
US3546680A (en) 1970-12-08
NL6906299A (fr) 1969-11-04
DE1922304A1 (de) 1969-11-13

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Legal Events

Date Code Title Description
TP Transmission of property
ST Notification of lapse