ES392443A1 - An input-output channel (i/o) willing to cooperate with the central treatment unit and the main memory of an electronic data processing system. (Machine-translation by Google Translate, not legally binding) - Google Patents
An input-output channel (i/o) willing to cooperate with the central treatment unit and the main memory of an electronic data processing system. (Machine-translation by Google Translate, not legally binding)Info
- Publication number
- ES392443A1 ES392443A1 ES392443A ES392443A ES392443A1 ES 392443 A1 ES392443 A1 ES 392443A1 ES 392443 A ES392443 A ES 392443A ES 392443 A ES392443 A ES 392443A ES 392443 A1 ES392443 A1 ES 392443A1
- Authority
- ES
- Spain
- Prior art keywords
- store
- data
- interface unit
- buffer
- byte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
Abstract
An I/O channel comprises a CPU interface unit and an I/O interface unit which operate concurrently and independently, the CPU interface unit to receive control data from the CPU, and the I/O interface unit to transfer data between I/O units and a main store in accordance with control data supplied by the CPU interface unit, whereby control data for a future data transfer is assembled in the CPU interface unit while a data transfer is taking place under the control of the I/O interface unit. The control data goes from CPU to CPU interface unit via a storage data register of the main store, there being one such register for each I/O channel (if more than one), but the storage address register of the main store is common to all I/O channels. The CPU interface unit has a data store and a data control store, and the I/O interface unit has an interface store, an address store, a count store and a buffer store, all these stores being associative stores with 3-state cells (though 2- state cells could be used), a primary and a secondary selector trigger per word location, the primaries and secondaries of a given store being connected as respective shift registers and with two input/output registers per store, Specifications 1,186,703 and 1,231,908 being referred to for details. Various fields of the input/output registers of the same and different stores are interconnected so that stores control themselves and each other, the I/O units and the main store address and data registers, using table-look-up operations. The data control store controls the data store. The data store receives from a channel control word the (main store) data address, data count, flags and command code, and also holds unit control words, and is connected to the I/O interface unit, including the address, buffer and count stores. The interface store controls itself, the other stores of the I/O interface unit and the main store, exchanges signals with I/O units as in Specification 1,264,095 (referred to), and maintains a count of the number of bytes in the buffer store. The count store holds a count of the number of bytes to be transferred between I/O unit and main store, and decrements it as transfer proceeds. The address store holds the main store address and increments it or decrements it as transfer proceeds. The buffer store acts as a buffer between I/O unit and main store, the primary and secondary selector triggers being connected as respective cyclic shift registers and indicating the next position available for storing a byte and the next position to be read out respectively. On input, each byte is stored twice in a respective word location of the buffer store, read-out to the main store being from either of the copies, avoiding the need for a crossover path (since the byte could be either byte of a main store half-word). On output, one byte is stored in each word of the buffer store, using the two possible positions alternately in successive word locations, or a stored bit in each byte may indicate which position is used. Fields of the two input/output registers of the address store are interconnected, as are fields of those of the count store. The address store includes a shift table. On input, the signals sent between the interface store and I/O-unit include "service in " and "service out" but time can be saved, in a modification, by using " service in " to set a service latch thus producing " service out " directly and setting an interlock latch which signals the appearance of " service in " to the interface store. The service latch is reset when " service in " drops but cannot be set again until the interlock latch has been reset by a signal from the interlock store provided for gating the byte from the I/O unit into the buffer store. The buffer store can be replaced by two stores which, on input, store input bytes alternately, each byte being duplicated in its respective word location in its respective buffer store, read-out to the main store being of one byte copy from each store simultaneously (or of a single byte from one store). The data control store in the CPU interface unit could alternatively be an associative read-only store. The buffer store could be a conventionally addressed store, the interface store holding and updating the addresses of the first and last bytes in the buffer store.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB3127870 | 1970-06-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES392443A1 true ES392443A1 (en) | 1973-10-01 |
Family
ID=10320731
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES392443A Expired ES392443A1 (en) | 1970-06-27 | 1971-06-19 | An input-output channel (i/o) willing to cooperate with the central treatment unit and the main memory of an electronic data processing system. (Machine-translation by Google Translate, not legally binding) |
Country Status (10)
Country | Link |
---|---|
JP (1) | JPS5118296B1 (en) |
BE (1) | BE766468A (en) |
CA (1) | CA935935A (en) |
CH (1) | CH526166A (en) |
DE (1) | DE2130299C3 (en) |
ES (1) | ES392443A1 (en) |
FR (1) | FR2095551A5 (en) |
GB (1) | GB1264096A (en) |
NL (1) | NL7108868A (en) |
SE (1) | SE360759B (en) |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2606295C3 (en) * | 1976-02-17 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Arrangement for the transmission of characters between peripheral units controllable via a multiplex channel and a main memory of a central processor |
GB2002936B (en) * | 1977-08-04 | 1982-04-28 | Honeywell Inf Systems | Data transfer control systems |
DE2845218C2 (en) * | 1978-10-17 | 1986-03-27 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Microprogram-controlled input / output device and method for performing input / output operations |
EP0021489A1 (en) * | 1979-06-08 | 1981-01-07 | Koninklijke Philips Electronics N.V. | Input/output channel for a high-speed computing system |
CA1162314A (en) * | 1979-12-07 | 1984-02-14 | Hideo Ota | Data input/output method and system |
AU555632B2 (en) * | 1982-03-12 | 1986-10-02 | Honeywell Information Systems Incorp. | Multiplexing central to peripheral control signals |
US4523310A (en) * | 1983-01-28 | 1985-06-11 | Gould Computer Systems Inc. | Synchronous communications multiplexer |
US7502873B2 (en) | 2006-10-10 | 2009-03-10 | International Business Machines Corporation | Facilitating access to status and measurement data associated with input/output processing |
US7500023B2 (en) | 2006-10-10 | 2009-03-03 | International Business Machines Corporation | Facilitating input/output processing by using transport control words to reduce input/output communications |
US8001298B2 (en) | 2008-02-14 | 2011-08-16 | International Business Machines Corporation | Providing extended measurement data in an I/O processing system |
US7904605B2 (en) | 2008-02-14 | 2011-03-08 | International Business Machines Corporation | Computer command and response for determining the state of an I/O operation |
US8176222B2 (en) | 2008-02-14 | 2012-05-08 | International Business Machines Corporation | Early termination of an I/O operation in an I/O processing system |
US7908403B2 (en) | 2008-02-14 | 2011-03-15 | International Business Machines Corporation | Reserved device access contention reduction |
US8196149B2 (en) | 2008-02-14 | 2012-06-05 | International Business Machines Corporation | Processing of data to determine compatability in an input/output processing system |
US8108570B2 (en) | 2008-02-14 | 2012-01-31 | International Business Machines Corporation | Determining the state of an I/O operation |
US7899944B2 (en) | 2008-02-14 | 2011-03-01 | International Business Machines Corporation | Open exchange limiting in an I/O processing system |
US9052837B2 (en) | 2008-02-14 | 2015-06-09 | International Business Machines Corporation | Processing communication data in a ships passing condition |
US8478915B2 (en) | 2008-02-14 | 2013-07-02 | International Business Machines Corporation | Determining extended capability of a channel path |
US7917813B2 (en) | 2008-02-14 | 2011-03-29 | International Business Machines Corporation | Exception condition determination at a control unit in an I/O processing system |
US7941570B2 (en) | 2008-02-14 | 2011-05-10 | International Business Machines Corporation | Bi-directional data transfer within a single I/O operation |
US8082481B2 (en) | 2008-02-14 | 2011-12-20 | International Business Machines Corporation | Multiple CRC insertion in an output data stream |
US7840718B2 (en) | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing of data to suspend operations in an input/output processing log-out system |
US8166206B2 (en) | 2008-02-14 | 2012-04-24 | International Business Machines Corporation | Cancel instruction and command for determining the state of an I/O operation |
US8095847B2 (en) | 2008-02-14 | 2012-01-10 | International Business Machines Corporation | Exception condition handling at a channel subsystem in an I/O processing system |
US7937507B2 (en) | 2008-02-14 | 2011-05-03 | International Business Machines Corporation | Extended measurement word determination at a channel subsystem of an I/O processing system |
US8312189B2 (en) | 2008-02-14 | 2012-11-13 | International Business Machines Corporation | Processing of data to monitor input/output operations |
US8214562B2 (en) | 2008-02-14 | 2012-07-03 | International Business Machines Corporation | Processing of data to perform system changes in an input/output processing system |
US7890668B2 (en) | 2008-02-14 | 2011-02-15 | International Business Machines Corporation | Providing indirect data addressing in an input/output processing system where the indirect data address list is non-contiguous |
US7840717B2 (en) * | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing a variable length device command word at a control unit in an I/O processing system |
US8117347B2 (en) | 2008-02-14 | 2012-02-14 | International Business Machines Corporation | Providing indirect data addressing for a control block at a channel subsystem of an I/O processing system |
US7904606B2 (en) | 2008-07-31 | 2011-03-08 | International Business Machines Corporation | Transport control channel program chain linked branching |
US8055807B2 (en) | 2008-07-31 | 2011-11-08 | International Business Machines Corporation | Transport control channel program chain linking including determining sequence order |
US7937504B2 (en) | 2008-07-31 | 2011-05-03 | International Business Machines Corporation | Transport control channel program message pairing |
US8332542B2 (en) | 2009-11-12 | 2012-12-11 | International Business Machines Corporation | Communication with input/output system devices |
RU2445675C1 (en) * | 2010-11-17 | 2012-03-20 | Леонид Павлович Коршунов | System to control data output |
RU2445673C1 (en) * | 2010-11-17 | 2012-03-20 | Леонид Павлович Коршунов | Device to control data output |
US8364853B2 (en) | 2011-06-01 | 2013-01-29 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8583988B2 (en) | 2011-06-01 | 2013-11-12 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8738811B2 (en) | 2011-06-01 | 2014-05-27 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US9021155B2 (en) | 2011-06-01 | 2015-04-28 | International Business Machines Corporation | Fibre channel input/output data routing including discarding of data transfer requests in response to error detection |
US8677027B2 (en) | 2011-06-01 | 2014-03-18 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8364854B2 (en) | 2011-06-01 | 2013-01-29 | International Business Machines Corporation | Fibre channel input/output data routing system and method |
US8473641B2 (en) | 2011-06-30 | 2013-06-25 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8346978B1 (en) | 2011-06-30 | 2013-01-01 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8312176B1 (en) | 2011-06-30 | 2012-11-13 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
US8549185B2 (en) | 2011-06-30 | 2013-10-01 | International Business Machines Corporation | Facilitating transport mode input/output operations between a channel subsystem and input/output devices |
RU2522025C1 (en) * | 2012-12-06 | 2014-07-10 | Тимофей Леонидович Коршунов | Data output control system |
RU2551807C2 (en) * | 2012-12-18 | 2015-05-27 | Леонид Павлович Коршунов | Data output control device |
US8918542B2 (en) | 2013-03-15 | 2014-12-23 | International Business Machines Corporation | Facilitating transport mode data transfer between a channel subsystem and input/output devices |
US8990439B2 (en) | 2013-05-29 | 2015-03-24 | International Business Machines Corporation | Transport mode data transfer between a channel subsystem and input/output devices |
-
1970
- 1970-06-27 GB GB1264096D patent/GB1264096A/en not_active Expired
-
1971
- 1971-04-29 BE BE766468A patent/BE766468A/en not_active IP Right Cessation
- 1971-04-29 FR FR7116466A patent/FR2095551A5/fr not_active Expired
- 1971-06-02 JP JP3790571A patent/JPS5118296B1/ja active Pending
- 1971-06-17 CA CA115870A patent/CA935935A/en not_active Expired
- 1971-06-18 SE SE795071A patent/SE360759B/xx unknown
- 1971-06-18 DE DE19712130299 patent/DE2130299C3/en not_active Expired
- 1971-06-19 ES ES392443A patent/ES392443A1/en not_active Expired
- 1971-06-21 CH CH900971A patent/CH526166A/en not_active IP Right Cessation
- 1971-06-25 NL NL7108868A patent/NL7108868A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE2130299A1 (en) | 1972-01-05 |
CH526166A (en) | 1972-07-31 |
GB1264096A (en) | 1972-02-16 |
SE360759B (en) | 1973-10-01 |
NL7108868A (en) | 1971-12-29 |
DE2130299B2 (en) | 1975-10-23 |
BE766468A (en) | 1971-09-16 |
FR2095551A5 (en) | 1972-02-11 |
JPS5118296B1 (en) | 1976-06-09 |
CA935935A (en) | 1973-10-23 |
DE2130299C3 (en) | 1978-09-21 |
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