ES2091840T3 - Circuito integrado que comprende una celula standard, una celula de aplicacion y una celula de prueba. - Google Patents
Circuito integrado que comprende una celula standard, una celula de aplicacion y una celula de prueba.Info
- Publication number
- ES2091840T3 ES2091840T3 ES91112697T ES91112697T ES2091840T3 ES 2091840 T3 ES2091840 T3 ES 2091840T3 ES 91112697 T ES91112697 T ES 91112697T ES 91112697 T ES91112697 T ES 91112697T ES 2091840 T3 ES2091840 T3 ES 2091840T3
- Authority
- ES
- Spain
- Prior art keywords
- cell
- integrated circuit
- application
- instruction
- standard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Stored Programmes (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
LA PRESENTE INVENCION SE REFIERE A UN CIRCUITO INTEGRADO QUE COMPRENDE UNA CELULA ESTANDAR (4), UNA CELULA DE APLICACION (2) Y UNA CELULA DE PRUEBA (3) PREVISTA EN PARTICULAR PARA GRABAR O PARA MODIFICAR DESDE EL EXTERIOR DEL CIRCUITO INTEGRADO EL VALOR DE SEÑALES DE COMUNICACION QUE TRANSITAN ENTRE ESTA CELULA ESTANDAR Y ESTA CELULA DE APLICACION. LA CELULA ESTANDAR QUE EJECUTA INSTRUCCIONES PROPORCIONADAS SOBRE UN BUS DE INSTRUCCION (3B4) POR UNA MEMORIA DE PROGRAMA LOCALIZADA EN LA CELULA DE APLICACION EN RESPUESTA A UNA DIRECCION DE INSTRUCCION TRANSPORTADA POR UN BUS DE DIRECCION DE INSTRUCCION (3A4), CONSTITUYENDO LOS CONDUCTORES DE ESTOS BUSES ENLACES DE COMUNICACION, ESTA CELULA DE PRUEBA COMPRENDE MEDIOS DE DERIVACION PARA SUSTITUIR UNA INSTRUCCION AL MENOS DE LA MEMORIA DE PROGRAMA POR UNA INSTRUCCION ERRONEA DE SUSTITUCION PREVIAMENTE GRABADA EN EL CIRCUITO INTEGRADO EN RESPUESTA A UN ESTADO DETERMINADO DE AL MENOS CIERTOS ENLACES DE COMUNICACION.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9009978A FR2665593A1 (fr) | 1990-08-03 | 1990-08-03 | Circuit integre comprenant une cellule standard, une cellule d'application et une cellule de test. |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2091840T3 true ES2091840T3 (es) | 1996-11-16 |
Family
ID=9399420
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES91112697T Expired - Lifetime ES2091840T3 (es) | 1990-08-03 | 1991-07-29 | Circuito integrado que comprende una celula standard, una celula de aplicacion y una celula de prueba. |
Country Status (9)
Country | Link |
---|---|
US (1) | US5309444A (es) |
EP (1) | EP0469507B1 (es) |
JP (1) | JP2878503B2 (es) |
AT (1) | ATE142802T1 (es) |
DE (1) | DE69122001T2 (es) |
DK (1) | DK0469507T3 (es) |
ES (1) | ES2091840T3 (es) |
FR (1) | FR2665593A1 (es) |
GR (1) | GR3021808T3 (es) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5408672A (en) * | 1991-11-18 | 1995-04-18 | Matsushita Electric Industrial Co. | Microcomputer having ROM to store a program and RAM to store changes to the program |
JPH07162435A (ja) * | 1993-12-06 | 1995-06-23 | Fujitsu Ltd | 半固定パス確認方法および装置 |
FR2720174B1 (fr) * | 1994-05-20 | 1996-08-14 | Sgs Thomson Microelectronics | Procédé pour tester le déroulement d'un programme d'instructions exécutées par un circuit intégré spécialisé, et circuit intégré spécialisé s'y rapportant. |
US7464044B2 (en) * | 1998-12-08 | 2008-12-09 | International Business Machines Corporation | Method and system for using emulation objects for developing point of sale |
JP2001051863A (ja) * | 1999-08-09 | 2001-02-23 | Fujitsu Ltd | マイクロプロセッサ |
EP1368670B1 (en) * | 2001-02-07 | 2005-03-23 | Koninklijke Philips Electronics N.V. | Test circuitry of an integrated circuit comprising only one selection element for each signal path |
US7356454B2 (en) * | 2003-10-17 | 2008-04-08 | Ud Technology Corporation | Method and apparatus for emulation of logic circuits |
US7755960B2 (en) * | 2007-12-17 | 2010-07-13 | Stmicroelectronics Sa | Memory including a performance test circuit |
CN113315662B (zh) * | 2021-05-28 | 2022-09-23 | 广州市炬元互联网科技有限公司 | 一种链路扫描分析***及方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4698588A (en) * | 1985-10-23 | 1987-10-06 | Texas Instruments Incorporated | Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit |
US4992934A (en) * | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US4819234A (en) * | 1987-05-01 | 1989-04-04 | Prime Computer, Inc. | Operating system debugger |
US4857835A (en) * | 1987-11-05 | 1989-08-15 | Texas Instruments Incorporated | Global event qualification system |
EP0628831B1 (en) * | 1988-09-07 | 1998-03-18 | Texas Instruments Incorporated | Bidirectional boundary scan test cell |
US5212693A (en) * | 1990-08-02 | 1993-05-18 | Ibm Corporation | Small programmable array to the on-chip control store for microcode correction |
-
1990
- 1990-08-03 FR FR9009978A patent/FR2665593A1/fr active Granted
-
1991
- 1991-07-29 DE DE69122001T patent/DE69122001T2/de not_active Expired - Fee Related
- 1991-07-29 DK DK91112697.7T patent/DK0469507T3/da active
- 1991-07-29 EP EP91112697A patent/EP0469507B1/fr not_active Expired - Lifetime
- 1991-07-29 AT AT91112697T patent/ATE142802T1/de not_active IP Right Cessation
- 1991-07-29 ES ES91112697T patent/ES2091840T3/es not_active Expired - Lifetime
- 1991-08-02 JP JP3282332A patent/JP2878503B2/ja not_active Expired - Lifetime
- 1991-08-02 US US07/739,544 patent/US5309444A/en not_active Expired - Fee Related
-
1996
- 1996-11-28 GR GR960403199T patent/GR3021808T3/el unknown
Also Published As
Publication number | Publication date |
---|---|
JPH05282895A (ja) | 1993-10-29 |
FR2665593A1 (fr) | 1992-02-07 |
GR3021808T3 (en) | 1997-02-28 |
EP0469507A1 (fr) | 1992-02-05 |
JP2878503B2 (ja) | 1999-04-05 |
DK0469507T3 (es) | 1997-01-20 |
DE69122001T2 (de) | 1997-02-06 |
FR2665593B1 (es) | 1994-08-19 |
DE69122001D1 (de) | 1996-10-17 |
US5309444A (en) | 1994-05-03 |
ATE142802T1 (de) | 1996-09-15 |
EP0469507B1 (fr) | 1996-09-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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