ES2074676T3 - Procedimiento y sistema de transmision numerica de datos en serie. - Google Patents
Procedimiento y sistema de transmision numerica de datos en serie.Info
- Publication number
- ES2074676T3 ES2074676T3 ES91401929T ES91401929T ES2074676T3 ES 2074676 T3 ES2074676 T3 ES 2074676T3 ES 91401929 T ES91401929 T ES 91401929T ES 91401929 T ES91401929 T ES 91401929T ES 2074676 T3 ES2074676 T3 ES 2074676T3
- Authority
- ES
- Spain
- Prior art keywords
- data
- transmission
- procedure
- series
- determination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 title abstract 5
- 210000000056 organ Anatomy 0.000 abstract 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- VJYFKVYYMZPMAB-UHFFFAOYSA-N ethoprophos Chemical group CCCSP(=O)(OCC)SCCC VJYFKVYYMZPMAB-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000003190 viscoelastic substance Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
LA TRANSMISION NUMERICA DE DATOS ES DEL TIPO QUE COMPRENDE LA ADICION DE UNA INFORMACION DE RELOJ Y DE SINCRONIZACION A LOS DATOS PARA CONSTITUIR LA SEÑAL DE TRANSMISION, Y LA DETERMINACION DEL CAUDAL DE TRANSMISION A PARTIR DE DICHA INFORMACION RECIBIDA. SEGUN LA INVENCION, DICHA INFORMACION CONSISTE EN LA SEÑAL DE TRANSMISION EN UN FRENTE DE SINCRONIZACION (SYNC) AÑADIDO A CADA GRUPO DE N BITS DE DATOS (D0-D7, OP) Y LA DETERMINACION DEL CAUDAL DE TRANSIIQ ON CONSISTE EN PRODUCIR N SEÑALES DE RELOJNTE Y DE MANERA SOLIDARIA SOBRE UN ORGANO DE SOPORTE (7) PARA FORMAR UN CONJUNTO UNITARIO AMOVIBLE APTO PARA ACOPLARSE AL EMISOR (1) POR MEDIOS QUE LE SON PROPIOS. EL DISPOSITIVO COMPRENDE TAMBIEN UN ELEMENTO DE TENSION (9), QUE CONTIENE CON EL ORGANO DE SOPORTE (7), EL MATERIAL VISCOELASTICO (8). APLICACION EN LOS MATERIALES DE INSONORIZACION.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9008811A FR2664770A1 (fr) | 1990-07-11 | 1990-07-11 | Procede et systeme de transmission numerique de donnees en serie. |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2074676T3 true ES2074676T3 (es) | 1995-09-16 |
Family
ID=9398588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES91401929T Expired - Lifetime ES2074676T3 (es) | 1990-07-11 | 1991-07-10 | Procedimiento y sistema de transmision numerica de datos en serie. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5268937A (es) |
EP (1) | EP0466591B1 (es) |
JP (1) | JP3032330B2 (es) |
CA (1) | CA2046234C (es) |
DE (1) | DE69109558T2 (es) |
ES (1) | ES2074676T3 (es) |
FR (1) | FR2664770A1 (es) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5490282A (en) * | 1992-12-08 | 1996-02-06 | International Business Machines Corporation | Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference |
US5724392A (en) * | 1993-10-04 | 1998-03-03 | Siemens Business Communication Systems, Inc. | Automatic path delay compensation system |
GB2287622B (en) * | 1994-03-17 | 1998-10-28 | Nissan Motor | Multiplex serial data communication circuit network and method and motor control system and method using multiplex serial data communication circuit network |
JP3130425B2 (ja) * | 1994-03-18 | 2001-01-31 | 富士通株式会社 | ジッタ抑圧回路 |
JPH0898284A (ja) * | 1994-07-25 | 1996-04-12 | Nippondenso Co Ltd | データ受信装置,送信装置および通信装置 |
FR2723494B1 (fr) * | 1994-08-04 | 1996-09-06 | Bull Sa | Procede d'echantillonnage d'un signal numerique en serie |
US5640523A (en) * | 1994-09-02 | 1997-06-17 | Cypress Semiconductor Corporation | Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery |
US5455540A (en) * | 1994-10-26 | 1995-10-03 | Cypress Semiconductor Corp. | Modified bang-bang phase detector with ternary output |
ATE265120T1 (de) * | 1994-12-09 | 2004-05-15 | Brent Townshend | Schnelles vermittlungssystem für analoge teilnehmeranschlüsse |
US5970103A (en) | 1996-09-06 | 1999-10-19 | Townshend; Brent | High speed communications system for analog subscriber connections |
US5832279A (en) * | 1995-06-07 | 1998-11-03 | Lsi Logic Corporation | Advanced programmable interrupt controller (APIC) with high speed serial data bus |
US5825824A (en) * | 1995-10-05 | 1998-10-20 | Silicon Image, Inc. | DC-balanced and transition-controlled encoding method and apparatus |
US5999571A (en) * | 1995-10-05 | 1999-12-07 | Silicon Image, Inc. | Transition-controlled digital encoding and signal transmission system |
US5974464A (en) * | 1995-10-06 | 1999-10-26 | Silicon Image, Inc. | System for high speed serial video signal transmission using DC-balanced coding |
JP2914267B2 (ja) * | 1996-01-30 | 1999-06-28 | 日本電気株式会社 | 集積回路のデータ転送方法およびその装置 |
US6108390A (en) * | 1997-03-07 | 2000-08-22 | Advanced Micro Devices, Inc. | Method of and apparatus for encoding of output symbol size |
DE19733748C2 (de) * | 1997-08-04 | 1999-07-15 | Bosch Gmbh Robert | Datenübertragungsvorrichtung |
JP3271602B2 (ja) * | 1999-02-17 | 2002-04-02 | 日本電気株式会社 | 半導体集積回路装置およびその設計方法 |
JP3814470B2 (ja) * | 2000-08-09 | 2006-08-30 | 富士通株式会社 | データ転送方法及びデータ転送装置 |
US6880026B2 (en) * | 2002-05-16 | 2005-04-12 | International Business Machines Corporation | Method and apparatus for implementing chip-to-chip interconnect bus initialization |
US6996650B2 (en) * | 2002-05-16 | 2006-02-07 | International Business Machines Corporation | Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus |
US7180949B2 (en) * | 2002-06-04 | 2007-02-20 | Lucent Technologies Inc. | High-speed chip-to-chip communication interface |
US7372928B1 (en) | 2002-11-15 | 2008-05-13 | Cypress Semiconductor Corporation | Method and system of cycle slip framing in a deserializer |
DE10344004A1 (de) * | 2003-09-23 | 2005-04-14 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Erzeugung einer internen Zeitbasis für eine Diagnosefunktion für einen Endstufenbaustein |
US8085857B1 (en) | 2003-09-25 | 2011-12-27 | Cypress Semiconductor Corporation | Digital-compatible multi-state-sense input |
US7526054B2 (en) * | 2005-03-04 | 2009-04-28 | Analog Devices, Inc. | Method, article, and apparatus for a dynamic phase delay compensator |
US7454543B2 (en) * | 2006-04-26 | 2008-11-18 | International Business Machines Corporation | Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus |
US7450039B2 (en) * | 2006-07-05 | 2008-11-11 | Silicon Library Inc. | Transmission device and electronic apparatus with self-diagnostic function, and self-diagnostic method for use therein |
US8832336B2 (en) * | 2010-01-30 | 2014-09-09 | Mosys, Inc. | Reducing latency in serializer-deserializer links |
US8509908B2 (en) | 2011-04-20 | 2013-08-13 | Cochlear Limited | Inter-chip communications for implantable stimulating devices |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3587043A (en) * | 1969-04-29 | 1971-06-22 | Rca Corp | Character parity synchronizer |
US3993957A (en) * | 1976-03-08 | 1976-11-23 | International Business Machines Corporation | Clock converter circuit |
JPS5630340A (en) * | 1979-08-20 | 1981-03-26 | Sony Corp | Digital signal transmitting method |
US4449119A (en) * | 1981-12-14 | 1984-05-15 | International Business Machines Corporation | Self-clocking serial decoder |
JPS59221047A (ja) * | 1983-05-30 | 1984-12-12 | Victor Co Of Japan Ltd | デイジタル信号伝送における同期信号検出回路 |
JPH0744448B2 (ja) * | 1986-03-31 | 1995-05-15 | 株式会社東芝 | デジタル位相同期ル−プ回路 |
US4922141A (en) * | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
US4873491A (en) * | 1987-10-19 | 1989-10-10 | Wilkins Jeffrey K | Phase shift circuit utilizing a variable time delay line |
US5022057A (en) * | 1988-03-11 | 1991-06-04 | Hitachi, Ltd. | Bit synchronization circuit |
JP2531742B2 (ja) * | 1988-05-17 | 1996-09-04 | 株式会社東芝 | 電圧制御発振回路 |
ATE101769T1 (de) * | 1988-10-13 | 1994-03-15 | Siemens Ag | Verfahren und schaltungsanordnung zum empfang eines binaeren digitalsignals. |
US5022056A (en) * | 1989-10-23 | 1991-06-04 | National Semiconductor Corporation | Method and structure for digital phase synchronization |
US5072407A (en) * | 1990-01-08 | 1991-12-10 | Gandalf Technologies, Inc. | Serial data rate detection method and apparatus |
US5079519A (en) * | 1991-02-14 | 1992-01-07 | Notorola, Inc. | Digital phase lock loop for a gate array |
-
1990
- 1990-07-11 FR FR9008811A patent/FR2664770A1/fr active Granted
-
1991
- 1991-07-04 CA CA002046234A patent/CA2046234C/fr not_active Expired - Fee Related
- 1991-07-09 US US07/727,430 patent/US5268937A/en not_active Expired - Lifetime
- 1991-07-10 EP EP91401929A patent/EP0466591B1/fr not_active Expired - Lifetime
- 1991-07-10 ES ES91401929T patent/ES2074676T3/es not_active Expired - Lifetime
- 1991-07-10 DE DE69109558T patent/DE69109558T2/de not_active Expired - Fee Related
- 1991-07-11 JP JP17134091A patent/JP3032330B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2664770A1 (fr) | 1992-01-17 |
CA2046234C (fr) | 1995-08-29 |
CA2046234A1 (fr) | 1992-01-12 |
DE69109558T2 (de) | 1995-09-28 |
JPH06343071A (ja) | 1994-12-13 |
FR2664770B1 (es) | 1994-12-16 |
EP0466591B1 (fr) | 1995-05-10 |
DE69109558D1 (de) | 1995-06-14 |
US5268937A (en) | 1993-12-07 |
JP3032330B2 (ja) | 2000-04-17 |
EP0466591A1 (fr) | 1992-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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