ES2023666B3 - Procedimiento y dispositivo de transmision de datos numericos. - Google Patents
Procedimiento y dispositivo de transmision de datos numericos.Info
- Publication number
- ES2023666B3 ES2023666B3 ES87402371T ES87402371T ES2023666B3 ES 2023666 B3 ES2023666 B3 ES 2023666B3 ES 87402371 T ES87402371 T ES 87402371T ES 87402371 T ES87402371 T ES 87402371T ES 2023666 B3 ES2023666 B3 ES 2023666B3
- Authority
- ES
- Spain
- Prior art keywords
- procedure
- transmission
- numerical data
- numerical
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8615134A FR2606239A1 (fr) | 1986-10-30 | 1986-10-30 | Procede et dispositif de transmission de donnees numeriques |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2023666B3 true ES2023666B3 (es) | 1992-02-01 |
Family
ID=9340370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES87402371T Expired - Lifetime ES2023666B3 (es) | 1986-10-30 | 1987-10-22 | Procedimiento y dispositivo de transmision de datos numericos. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4811361A (es) |
EP (1) | EP0269481B1 (es) |
JP (1) | JPH0744570B2 (es) |
DE (1) | DE3770591D1 (es) |
ES (1) | ES2023666B3 (es) |
FR (1) | FR2606239A1 (es) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01166632A (ja) * | 1987-12-22 | 1989-06-30 | Mitsubishi Electric Corp | ディジタル信号の復号方法及びその回路 |
JP2974678B2 (ja) * | 1988-06-23 | 1999-11-10 | ソニー株式会社 | データ誤り検出方式 |
US4939735A (en) * | 1988-07-21 | 1990-07-03 | International Business Machines Corporation | Information handling system having serial channel to control unit link |
US4965883A (en) * | 1988-08-24 | 1990-10-23 | Digital Equipment Corporation | Method and apparatus for transmitting and receiving characters using a balanced weight error correcting code |
US4996690A (en) * | 1988-08-26 | 1991-02-26 | Stac Electronics | Write operation with gating capability |
GB8912471D0 (en) * | 1989-05-31 | 1989-07-19 | Int Computers Ltd | Data transmission code |
AU618680B2 (en) * | 1989-07-17 | 1992-01-02 | Digital Equipment Corporation | Data and forward error control coding techniques for digital signals |
US5144304A (en) * | 1989-07-17 | 1992-09-01 | Digital Equipment Corporation | Data and forward error control coding techniques for digital signals |
US5068854A (en) * | 1989-09-12 | 1991-11-26 | Cupertino, California U.S.A. | Error detection for fiber distributed interfaced optic link |
US5142530A (en) * | 1989-10-16 | 1992-08-25 | International Business Machines Corporation | Multi-frame stripping protocol for token ring networks |
US5146461A (en) * | 1989-11-13 | 1992-09-08 | Solbourne Computer, Inc. | Memory error correction system distributed on a high performance multiprocessor bus and method therefor |
EP0453863A2 (en) * | 1990-04-27 | 1991-10-30 | National Semiconductor Corporation | Methods and apparatus for implementing a media access control/host system interface |
GB2247138B (en) * | 1990-06-29 | 1994-10-12 | Digital Equipment Corp | System and method for error detection and reducing simultaneous switching noise |
US5625644A (en) * | 1991-12-20 | 1997-04-29 | Myers; David J. | DC balanced 4B/8B binary block code for digital data communications |
EP0562251A2 (en) * | 1992-03-24 | 1993-09-29 | Universities Research Association, Inc. | Parallel data transfer network controlled by a dynamically reconfigurable serial network |
US5331315A (en) * | 1992-06-12 | 1994-07-19 | Universities Research Association, Inc. | Switch for serial or parallel communication networks |
US5428611A (en) * | 1993-05-28 | 1995-06-27 | Digital Equipment Corporation | Strong framing protocol for HDLC and other run-length codes |
JPH0764886A (ja) * | 1993-08-23 | 1995-03-10 | Nec Corp | シリアルインターフェイス装置を有する処理装置 |
US5504929A (en) * | 1993-11-17 | 1996-04-02 | Adobe Systems Incorporated | Method and apparatus for encoding byte sequence for self-clocked high speed data transfer from a parallel port |
US5640523A (en) * | 1994-09-02 | 1997-06-17 | Cypress Semiconductor Corporation | Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery |
US5455540A (en) * | 1994-10-26 | 1995-10-03 | Cypress Semiconductor Corp. | Modified bang-bang phase detector with ternary output |
US5666468A (en) * | 1994-12-02 | 1997-09-09 | Grumman Corporation | Neural network binary code recognizer |
WO1997034397A1 (en) * | 1996-03-11 | 1997-09-18 | Hewlett-Packard Company | Apparatus and method for multi-level transmission of data |
US6477200B1 (en) * | 1998-11-09 | 2002-11-05 | Broadcom Corporation | Multi-pair gigabit ethernet transceiver |
WO2001041340A1 (en) * | 1999-11-30 | 2001-06-07 | Future Tv Technologies, Ltd. | Method and apparatus for transmission of source-routed data |
US6671316B1 (en) * | 2000-04-13 | 2003-12-30 | Storage Technology Corporation | Three state pulse width modulation code |
JP3639184B2 (ja) | 2000-04-18 | 2005-04-20 | 日本電信電話株式会社 | 通信システムにおける制御情報の符号化方法 |
FR2810479B1 (fr) * | 2000-06-14 | 2002-10-25 | Commissariat Energie Atomique | Procede de transmission de donnees avec code correcteur autosynchronise, codeur et decodeur autosynchronises, emetteur et recepteur correspondants |
US7031249B2 (en) * | 2000-10-27 | 2006-04-18 | Sharp Laboratories Of America, Inc. | Outer code for CSMA systems using an OFDM physical layer in contention-free mode |
US7024653B1 (en) * | 2000-10-30 | 2006-04-04 | Cypress Semiconductor Corporation | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) |
CA2376971A1 (en) * | 2001-03-16 | 2002-09-16 | Silicon Image, Inc. | Combining a clock signal and a data signal |
US6944804B1 (en) * | 2001-06-06 | 2005-09-13 | Silicon Image, Inc. | System and method for measuring pseudo pixel error rate |
JP2003143242A (ja) * | 2001-11-01 | 2003-05-16 | Hitachi Ltd | データ通信方法及びデータ通信装置 |
US6690309B1 (en) | 2001-12-17 | 2004-02-10 | Cypress Semiconductor Corporation | High speed transmission system with clock inclusive balanced coding |
US20030172178A1 (en) * | 2002-03-08 | 2003-09-11 | Eduard Lecha | Method to avoid high-level data link control (HDLC) frame abortion |
FR2837970A1 (fr) * | 2002-03-29 | 2003-10-03 | France Telecom | Procede de traduction de donnees au moyen d'un transducteur unique |
US7623586B2 (en) * | 2002-10-23 | 2009-11-24 | Panasonic Corporation | Frequency and phase control apparatus and maximum likelihood decoder |
US7372928B1 (en) | 2002-11-15 | 2008-05-13 | Cypress Semiconductor Corporation | Method and system of cycle slip framing in a deserializer |
US8085857B1 (en) | 2003-09-25 | 2011-12-27 | Cypress Semiconductor Corporation | Digital-compatible multi-state-sense input |
US6897793B1 (en) * | 2004-04-29 | 2005-05-24 | Silicon Image, Inc. | Method and apparatus for run length limited TMDS-like encoding of data |
RU2405217C2 (ru) * | 2005-01-31 | 2010-11-27 | Скайп Лимитед | Способ взвешенного сложения с перекрытием |
US7676725B1 (en) | 2006-02-27 | 2010-03-09 | The United States Of America As Represented By The Director, National Security Agency | Method of code generation that minimizes error propagation |
US7890061B2 (en) * | 2006-06-27 | 2011-02-15 | Intel Corporation | Selective 40 MHz operation in 2.4 GHz band |
US8201071B2 (en) * | 2006-11-15 | 2012-06-12 | Qimonda Ag | Information transmission and reception |
US8904258B2 (en) * | 2010-09-07 | 2014-12-02 | Zephyr Photonics | Modulation-forward error correction (MFEC) codes and methods of constructing and utilizing the same |
US10958348B2 (en) | 2012-12-29 | 2021-03-23 | Zephyr Photonics Inc. | Method for manufacturing modular multi-function active optical cables |
US9468085B2 (en) | 2012-12-29 | 2016-10-11 | Zephyr Photonics Inc. | Method and apparatus for implementing optical modules in high temperatures |
US9160452B2 (en) | 2012-12-29 | 2015-10-13 | Zephyr Photonics Inc. | Apparatus for modular implementation of multi-function active optical cables |
US9190809B2 (en) | 2012-12-29 | 2015-11-17 | Zephyr Photonics Inc. | Method and apparatus for active voltage regulation in optical modules |
US9728936B2 (en) | 2012-12-29 | 2017-08-08 | Zephyr Photonics Inc. | Method, system and apparatus for hybrid optical and electrical pumping of semiconductor lasers and LEDs for improved reliability at high temperatures |
US9172462B2 (en) * | 2012-12-31 | 2015-10-27 | Zephyr Photonics Inc. | Optical bench apparatus having integrated monitor photodetectors and method for monitoring optical power using same |
RU2642803C1 (ru) * | 2017-01-18 | 2018-01-26 | Евгений Тимофеевич Дюндиков | Способ повышения достоверности передачи цифрового сообщения |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1250908A (es) * | 1968-12-13 | 1971-10-27 | ||
US4146909A (en) * | 1977-11-21 | 1979-03-27 | International Business Machines Corporation | Sync pattern encoding system for run-length limited codes |
JPS5625849A (en) * | 1979-08-10 | 1981-03-12 | Hitachi Ltd | Coding system |
JPS5665313A (en) * | 1979-10-29 | 1981-06-03 | Sony Corp | Data converting circuit |
JPS5753802A (en) * | 1980-09-16 | 1982-03-31 | Toshiba Corp | Processor of digital signal |
FR2495858A1 (fr) * | 1980-12-05 | 1982-06-11 | Thomson Csf | Procede de transcodage parallele serie d'un train numerique parallele et dispositif de transmission de signaux video numerises mettant en oeuvre un tel procede |
US4544962A (en) * | 1981-07-06 | 1985-10-01 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for processing binary data |
JPS58168347A (ja) * | 1982-03-29 | 1983-10-04 | Mitsubishi Electric Corp | 同期符号検出回路 |
US4486739A (en) * | 1982-06-30 | 1984-12-04 | International Business Machines Corporation | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code |
US4569050A (en) * | 1983-01-14 | 1986-02-04 | Honeywell Inc. | Data communication system with fixed weight error correction and detection code |
JPS59231713A (ja) * | 1983-06-14 | 1984-12-26 | Sony Corp | 同期回路 |
WO1985001402A1 (en) * | 1983-09-19 | 1985-03-28 | Storage Technology Partners Ii | Sync pattern encoding system for data sectors written on a storage medium |
JPS6074854A (ja) * | 1983-09-30 | 1985-04-27 | Nec Corp | 符号伝送方式 |
JPH0721942B2 (ja) * | 1984-10-11 | 1995-03-08 | ソニー株式会社 | チヤンネル符号化方法 |
-
1986
- 1986-10-30 FR FR8615134A patent/FR2606239A1/fr not_active Withdrawn
-
1987
- 1987-10-22 ES ES87402371T patent/ES2023666B3/es not_active Expired - Lifetime
- 1987-10-22 DE DE8787402371T patent/DE3770591D1/de not_active Expired - Lifetime
- 1987-10-22 EP EP87402371A patent/EP0269481B1/fr not_active Expired - Lifetime
- 1987-10-28 JP JP62272904A patent/JPH0744570B2/ja not_active Expired - Lifetime
- 1987-10-29 US US07/114,202 patent/US4811361A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63129750A (ja) | 1988-06-02 |
FR2606239A1 (fr) | 1988-05-06 |
EP0269481B1 (fr) | 1991-06-05 |
JPH0744570B2 (ja) | 1995-05-15 |
US4811361A (en) | 1989-03-07 |
DE3770591D1 (de) | 1991-07-11 |
EP0269481A1 (fr) | 1988-06-01 |
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