Classifications

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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
  • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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  • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
  • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L29/107—Substrate region of field-effect devices
  • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
  • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
  • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42356—Disposition, e.g. buried gate electrode
  • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
  • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• • H—ELECTRICITY
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  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
  • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L29/2003—Nitride compounds

Definitions

• the invention relates to heterojunction transistors, and in particular heterojunction transistors with a vertical structure.
• heterojunction field effect transistors also referred to as heterostructure field effect transistors.
• Such transistors include in particular the high electron mobility transistors known as HEMTs.
• a high electron mobility transistor includes the superposition of two semiconductor layers having different forbidden bands which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons. For reasons of resistance to high voltage and temperature, these transistors are chosen so as to have a wide band of forbidden energy.
• heterojunction transistors The most common architecture for heterojunction transistors is based on a vertical stack of semiconductor layers on a substrate. Such a transistor is said to have a lateral structure, the source, the drain and the control gate of the transistor being arranged in its upper part with the source and the drain positioned on either side of the gate.
• a lateral transistor requires a large space to have a sufficiently large electron gas layer.
• a side transistor occupies a high surface of the substrate, such transistors are limited in size: the defect rate in a semiconductor material used to form the electron gas layer is problematic for transistors with a surface exceeding about 50 mm 2 . Beyond this surface, the proportion of transistors failing during the manufacturing process greatly affects its profitability.
• the source and the drain necessary for a high current density occupy a significant proportion of this substrate surface, which further limits the available width for the electron gas layer.
• heterojunction transistors with vertical structure have been developed.
• the 'Vertical Gallium Nitride transistors with buried p-type current blocking' document published on May 21, 2015 by the University of Santa Barbara, California, by Dr. Ramya Yeluri in Applied Physics Letter Volume 106, describes an example of a configuration of a heterojunction transistor with a vertical structure.
• This transistor comprises a first layer of GaN, N-doped on the rear face. A metal drain is formed under this first layer of GaN.
• This first layer of GaN is surmounted by a second layer of GaN, doping N type with a lower concentration.
• the second layer of GaN is surmounted by a third layer of GaN, P-type doping.
• the second layer forms an extension through the third layer, this extension being designated by the term "opening".
• the third layer of GaN is surmounted by a fourth layer of GaN, of unintentionally doped type.
• the opening is in contact with this fourth layer of GaN. Due to the presence of the third pGaN layer under the fourth GaN layer, the voltage breakdown resistance is ensured not only by the thickness of the second layer but also by the length of the fourth layer between the source and the opening, thus reducing the amplitude of the electric field in the GaN between the source and the drain.
• the fourth layer of GaN is surmounted by a layer of AIGaN, so as to form a layer of electron gas near their interface.
• a grid insulator is formed on the AIGaN layer directly above the opening. This grid insulator is surmounted by the metal grid. Sources are formed on either side of the grid, offset laterally with respect to the opening. The sources are in electrical contact with the electron gas layer. Since the conduction path uses a large part of the transistor surface, a large current density can be obtained for a smaller substrate area than with a side structure transistor. The leakage currents between source and drain in the off state are also reduced. Moreover, the postponement of the drain on the rear face makes it possible to reduce the surface of the transistor on the substrate.
• the method of manufacturing such a transistor includes the epitaxial growth deposition of the first to third layers.
• the substrate is then removed from the epitaxial reactor, and then an etching step is performed through the third layer to form a groove, until reaching the second layer.
• the substrate is then reintroduced into the epitaxial rector to grow the aperture, the fourth layer, and the AIGaN layer.
• the source and the grid are formed. Due to the exit of the epitaxial reactor substrate, the bottom of the throat undergoes a pollution requiring a cleaning step before beginning the epitaxial growth of the opening.
• Such a manufacturing process is therefore relatively complex and may lead to discontinuities during epitaxial deposition at the bottom of the groove.
• the on-state resistance of such a transistor is still relatively high, despite the use of a heterojunction conduction between the source and the plumb of the grid.
• US2008 / 0128862 discloses a heterojunction field effect transistor.
• a drain is provided on the rear face against a lower layer of semiconductor material.
• a separating layer of semiconductor material is provided on the lower layer.
• An element passes through the separation layer and is in contact with the lower layer.
• a source is formed in electrical contact with a layer of electron gas, and a gate is formed between the source and the through element.
• Such a transistor has limited performance, including a relatively low conduction current density.
• the invention aims to solve one or more of these disadvantages.
• the invention thus relates to a heterojunction field effect transistor and a method of manufacture, as defined in the appended independent claims.
• the invention also relates to the variants of the dependent claims. It will be understood by those skilled in the art that each of the features of the variants of the dependent claims may be independently combined with the features of the independent claims, without necessarily constituting an intermediate generalization.
• FIG 1 is a schematic cross sectional view of an example heterojunction transistor according to a first embodiment of the invention
• FIG. 2 is a diagram illustrating an example of current density in the on state of the transistor of FIG. 1;
• FIG. 3 is a schematic cross-sectional view of an example of a heterojunction transistor according to a second embodiment of the invention;
• FIG. 4 is a schematic cross-sectional view of an example of a heterojunction transistor according to a third embodiment of the invention.
• FIG. 5 is a schematic cross-sectional view of an example of a heterojunction transistor according to a fourth embodiment of the invention.
• FIGS. 6 to 12 illustrate various steps of an exemplary method of manufacturing the heterojunction transistor according to the fourth embodiment of the invention.
• FIG. 13 is a schematic cross-sectional view of an example of a heterojunction transistor according to a fifth embodiment of the invention.
• FIG. 14 is a schematic cross-sectional view of an example of a heterojunction transistor according to a sixth embodiment of the invention.
• FIG. 15 is a schematic cross-sectional view of an example of a heterojunction transistor according to a seventh embodiment of the invention.
• FIG. 16 is a schematic cross sectional view of an example of a heterojunction transistor according to an eighth embodiment of the invention.
• FIG. 17 is a schematic cross sectional view of an exemplary heterojunction transistor according to an eighth embodiment of the invention.
• FIG. 1 is a schematic cross sectional view of an example of a heterojunction transistor 1 according to a first embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• the transistor 1 comprises a substrate 10.
• the substrate 10 may for example be an electrical insulator or an intrinsic silicon or p-doped semiconductor material.
• the substrate 10 may, for example, be of silicon type with a mesh orientation (1 1 1 ).
• the substrate 10 may also be silicon carbide, ⁇ 2 ⁇ 3 or diamond. Such substrates advantageously make it possible to grow GaN layers by epitaxy.
• the substrate 10 may typically have a thickness of the order of 650 ⁇ , typically between 500 ⁇ and 2mm.
• the transistor 1 here advantageously comprises one (or more) matching layer (not shown) disposed on the substrate 10.
• the adaptation layer may be deposited in a manner known per se on the substrate 10, and serves as an intermediate between the substrate 10 and a layer of semiconductor material January 1, to allow mesh matching between the substrate 10 and the layer 1 January.
• the matching layer may typically be aluminum nitride.
• the layer 1 1 may have a buffer function to manage the mechanical stresses related to its possible difference in mesh parameters with the substrate 10.
• the layer 11 can be made via the use of a III-N semiconductor material, such as unintentionally doped GaN.
• the layer 1 1 may also advantageously be made of semiconductor material having N-type doping, for example N-doped GaN (with a dopant concentration, for example between 1 ⁇ 10 16 cm -3 and 5 ⁇ 10 16 cm -3 ). .
• the transistor 1 comprises a separation layer 12 formed on the layer 1 January.
• This separation layer 12 is here made of a III-V alloy type semiconductor material (for example a type III-V binary alloy, for example element III nitride, typically GaN).
• the transistor 1 comprises a layer 13 of semiconductor material of the III-V alloy type (for example a binary alloy of the III-V type, for example element III nitride, typically GaN) disposed on the layer 12.
• III-V alloy type for example a binary alloy of the III-V type, for example element III nitride, typically GaN
• the transistor 1 further comprises a layer 14 of semiconductor material of the III-V alloy type (for example a ternary alloy of the III-V type, for example element III nitride, typically AIGaN or ⁇ , or alternatively a quaternary alloy of element III nitride, for example of AlxGaylnci-x-yjN, keeping a greater band gap than that of the material of the layer 13).
• the layer 14, typically called the barrier layer can typically have a thickness of between 10 nm and 40 nm, for example 25 nm.
• the semiconductor layers 13 and 14 are superimposed in a manner known per se to form a layer of electron gas 15 at the interface or near the interface between these layers 13 and 14.
• the transistor 1 comprises an upper conduction electrode 21, comparable to the source.
• the electrode 21 is here formed on the layer 14 and forms an electrical contact with the electron gas layer 15.
• the electrical contact between the electrode 21 and the electron gas layer 15 is here formed by a zone of diffusion 210 of the metal of the electrode 21 in the layer 14.
• the transistor 1 comprises a lower conduction electrode 22, comparable to the drain.
• the electrode 22 is in electrical contact with a lower face of the layer 1 January.
• the electrode 22 is here housed in a recess 101 formed in the substrate 10. Such a configuration makes it possible to benefit from the rigidity of the substrate 10 to stiffen the entire transistor.
• the transistor 1 comprises a control gate 23 offset laterally with respect to the electrode 21.
• the control gate 23 is here configured to forming a normally open type transistor, the control gate 23 being here of the type formed in a recess through the layer 14.
• the control gate 23 is configured to selectively isolate and electrically connect two portions 151 and 152 of the gas layer
• the control gate 23 is here formed in a recess interrupting the electron gas layer 15.
• the control gate 23 comprises a gate insulator 234 covering the side walls and the bottom of this recess.
• the control gate 23 includes a gate metal 233 provided on the gate insulator 234 and in this recess. In the absence of bias on the control gate 23, the conduction under this control gate is interrupted. When applying a bias exceeding the threshold voltage on the control gate 23, the conduction under the control gate 23 is carried out via the layer 13.
• the transistor 1 further comprises a conductive element 24.
• the control gate 23 is positioned between the conductive element 24 and the conduction electrode 21.
• the conductive element 24 is in electrical contact with the portion 152 of the electron gas layer 15.
• the conductive element 24 passes through the separation layer 12 to be in contact with the layer 1 January.
• the conductive element 24 electrically connects the layer 1 1 with the portion 152 of the electron gas layer.
• the conductive element 24 here comprises a conductive layer 241 covering the side walls and the bottom of a groove. The remainder of the groove is here filled with another material 242, formed on the conductive layer 241.
• the other material 242 may be of dielectric or conductive type.
• the separation layer 12 is made of P-type doped semiconductor material, the layers 11 and 13 being either of unintentionally doped type or of N type doping.
• the layer 13 forms a separation between the layer 14 and the separation layer 12.
• the conduction path in the on state extends from the electrode 21, passing through the portion 151, the layer 13 between the parts 151 and 152, the portion 152, the conductive element 24, the thickness of the layer 1 1 and the electrode 22.
• the conduction in the conducting state between the conduction electrode 21 and the conductive element 24 being essentially ensured by the electron gas layer 15, this length affects only moderately the resistance to the on state of transistor 1.
• the transistor 1 behaves as a lateral transistor between the electrode 21 and the conductive element 24, and as a vertical transistor between the conductive element 24 and the electrode 22.
• a high dopant concentration can be used in the layer 12 without altering the on-state resistance of the transistor, thereby enhancing the voltage breakdown resistance of the transistor 1 .
• Such a configuration of the Transistor with the electrode 22 offset on the rear panel further allows to retain the advantages of a reduced surface area of the occupied substrate.
• the separation layer 12 extending from the electrode 21 to the conductive element 24, passing under the control gate 23, makes it possible to benefit from the length of the layer 13 in the plumb to participate in the resistance to breakdown. voltage in the off state of transistor 1.
• the separation layer 12 also serves to prevent a leakage current between the conduction electrode 21 and the conduction electrode 22 in the off state of the transistor 1.
• the separating layer 12 is here in contact with the semiconductor element 24 over a whole circumference thereof.
• the conductive element 24 advantageously has a width of 100 nm or more.
• the conductive element 24 advantageously has a depth of between 200 and 500 nanometers.
• the conductive element 24 advantageously has a width-to-depth ratio of between 0.2 and 0.5, in particular to promote the filling of the groove by the conductive layer.
• the distance between the conductive element 24 and the control gate 23 is advantageously at least equal to 2 ⁇ . Because of a small distance between the conductive element 24 and the conduction electrode 22 (detailed below), the between the conductive element 24 and the control gate 23 is advantageously increased to increase the voltage withstand of the transistor 1.
• the conductive element 24 penetrates into the semiconductor layer 1 1 advantageously with a depth of at least 10 nm, preferably between 50 and 100 nanometers. Exceeding the conductive element
• At least a portion of the conduction electrode 22 is positioned in line with the conductive element 24.
• the layer 1 1 is for example GaN type unintentionally doped or having reduced concentration N type doping.
• the layer 1 1 may be N type GaN having a dopant concentration between 1 x10 16 cm -3 and
• the layer 12 may typically have a thickness of 30 nm to 150 nm.
• the layer 12 is advantageously P-doped GaN with a concentration in the range of 1 ⁇ 10 17 cm -3 and 3 ⁇ 10 17 cm -3 .
• the layer 13 may for example have a thickness typically between 50 and 200 nm.
• the semiconductor material of the layer 13 may be identical to that of the layer 11.
• the material of the electrode 21 is, for example, titanium, aluminum, or an alloy of titanium and aluminum.
• the material of the electrode 21 is advantageously identical to that of the metal layer 241 of the conductive element 24.
• the same deposition step can be used to form the metal of the electrode 21 and the metal layer 241.
• the electrodes 21 and 22 may use the same metal.
• the electrical contact between the electron gas layer 15 and the conduction electrode 21 can be realized laterally, for example if the conduction electrode 21 is formed in a recess passing through the layer 14 and reaching layer 13.
• Transistor 1 is here of normally open type, obtained by interruption of the electron gas layer by a recess in the layer 14.
• Other variants of normally open type transistor may of course be made, for example transistors comprising implantations of dopants directly above the channel zone.
• FIG. 2 is a diagram illustrating an example of current density in the on state of transistor 1, in the sectional view of FIG. 1.
• FIG. 3 is a schematic cross sectional view of an example of a heterojunction transistor 1 according to a second embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• the transistor 1 here has sources and gratings split on either side of a conductive element 24.
• the transistor 1 of the second embodiment takes up the substrate 10 and the stack of layers 1 1 to 14 with the same thicknesses and compositions as described for the first embodiment.
• the conductive element 24 is identical to that of the first embodiment.
• a conduction electrode 21 1 is identical to the conduction electrode 21 of the first embodiment.
• a gate 231 is identical to the control gate 23 of the first embodiment.
• the transistor 1 here comprises another control gate 232.
• the control gate 232 has the same structure as the control gate 231 and is positioned symmetrically to the control gate 231 with respect to the conductive element 24.
• the control gate 232 is thus configured to selectively isolate and electrically connect two portions of the electron gas layer 15.
• the control gate 232 is also formed in a recess interrupting the electron gas layer 15.
• Transistor 1 also includes another conduction electrode
• the conduction electrode 212 has the same structure as the conduction electrode 21 1 and is positioned symmetrically with the conduction electrode 21 1 with respect to the conductive element 24.
• the conduction electrode 212 is electrically connected to the electron gas layer 15.
• the control gate 232 is thus positioned between the conductive element 24 and the conduction electrode 212.
• the drain 22 is here positioned in line with the conductive element 24, and is centered with respect to this conductive element 24.
• the conduction path in the on state extends:
• the electrode 21 1 passing through the part 151, the layer 13 between the parts 151 and 152, the part 152, the conductive element 24, the thickness of the layer 1 1 and the electrode 22;
• the electrode 212 passing through the electron gas layer 15, the layer 13 under the gate 232, the electron gas layer 15, the conductive element 24, the thickness of the the layer 1 1 and the electrode 22.
• FIG. 4 is a schematic cross-sectional view of an example of a heterojunction transistor 1 according to a third embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• Transistor 1 of the third embodiment has a structure substantially identical to that of transistor 1 of the second embodiment.
• the transistor 1 of the third embodiment differs from that of the second embodiment as follows:
• the transistor 1 here has elements 16 of semiconductor material and having the same type of doping as the separation layer 12.
• the elements 16 are for example made of the same material as the separation layer 12.
• the elements 16 connect the layer 14 to the separation layer 12.
• the elements 16 thus pass through the layer 13.
• An element 16 is positioned vertically above the conduction electrode 21 1 and connected to the potential of the conduction electrode 21 1, another element 16 being positioned vertically above the electrode conduction electrode 212 and connected to the potential of the conduction electrode 212. In this embodiment, it is thus possible to polarize the separation layer 12 to the potential of the conduction electrodes 21 1 and 212.
• FIG. 5 is a schematic cross-sectional view of an example of a heterojunction transistor 1 according to a fourth embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• Transistor 1 of the fourth embodiment has a structure substantially identical to that of transistor 1 of the second embodiment.
• the transistor 1 of the third embodiment differs from that of the second embodiment as follows: the separation layer 12 is here formed of a dielectric material. The leakage currents to the substrate in the open state of the transistor are thus substantially reduced.
• Figures 6 to 12 illustrate various steps of an exemplary manufacturing method for a transistor 1 according to the fourth embodiment.
• FIG. 6 gives a substrate 10 surmounted by a stack of layers of semiconductor material 11, 12, 13 and 14.
• the layers 11 to 14 are typically produced in a manner known per se, for example by means of Epitaxial growth steps (MOCVD type for chemical vapor deposition from organometallic compounds) of the different layers.
• the epitaxial growth deposits can be made without removing the substrate from the epitaxy reactor.
• the layer 1 1 is here a GaN layer of unintentionally doped type, the layer 12 and a P type doped GaN layer, the layer 13 is a GaN layer of unintentionally doped type, and the layer 14 is a layer of AIGaN.
• the layers 1 1 to 14 may have the dopant thicknesses and concentrations described with reference to the fourth embodiment. By superposing the layers 13 and 14, a layer of electron gas 15 is obtained in a manner known per se close to their interface.
• an etching step (typically by means of preliminary non-detailed masking and photolithography steps) of a groove 240 is carried out through the layers 12, 13 and 14 (and therefore the gas layer). of electrons 15). Etching is continued here to extend the groove 240 in the layer 1 January. The etching is in particular continued to ensure that the groove 240 passes through the layer 12, and so that the distance between the bottom of the groove 240 and the bottom of the layer 1 1 is at most equal to 1 ⁇ . Such an engraving can be performed without a stop layer, by identifying a change of species etched during the process.
• the conduction electrode 21 1 (and the split conduction electrode 212) is metallized by depositing metal on the layer 14 and then shaping it.
• the metallization of the conductive element 24 was also carried out by depositing the metal layer 241 on the side walls and the bottom of the groove 240 in particular, and then shaping it.
• the metal layer 241 formed on the side walls of the groove 240 then provides electrical conduction between the electron gas layer 15 and the layer 1 January.
• the same metal deposition has been carried out for the conduction electrodes 21 1, 212 and for the conductive element 24, and then proceeded to the same shaping step.
• the method of manufacturing a transistor according to the invention is then substantially simplified.
• the metallization of the conduction electrode 21 (and / or the electrode 212 and the metal layer 241) may comprise the deposition of metals such as Ti, Al, AlCu or Ta.
• the metallization may comprise the deposition of several metal layers, for example a superposition of layers of several metals.
• the metallization can for example comprise the deposition of a superposition of layers of Ti and Al, Ti and AICu, or a superposition of layers of Ta and Al. For example, it is possible to deposit:
• an annealing step has been carried out in order to make an ohmic contact between the conduction electrodes 21 1 and 212, and the electron gas layer 15, through the layer 14.
• the annealing will be performed at a temperature between 500 ° and 600 ° C, for a period of between ten seconds and two minutes.
• the annealing will advantageously be carried out at temperatures below 650 ° C., in order to avoid risking a deep diffusion of the Ti or Ta in the stack of semiconductor layers, which could affect the vertical voltage withstand of the transistor 1 under the electrodes 21 1 and 212.
• annealing at 600 ° C under nitrogen for about 15 seconds induces the formation of TiN in layer 14, to form a connection with the gas layer. electrons 15.
• a formation step (typically by means of etching preceded by non-detailed masking and photolithography steps) of grooves 230, on either side and away from the element, is carried out. 24.
• the grooves 230 are here formed through the layer 14 to reach the layer 13 and thus interrupt the layer of electron gas 15.
• the gas layer of electrons 15 is here separated into a portion 151 in electrical contact with a conduction electrode 21 1 or 212, and a portion 152 in electrical contact with the conductive element 24.
• a dielectric layer 234 has been formed, in particular on the walls and on the bottom of the grooves 230.
• the dielectric layer 234 is for example deposited by a method of the ALD (layer deposition) type. atomic), favoring its crystalline quality.
• the dielectric 234 may be any type of dielectric used as control gate insulator.
• the dielectric layer 234 may for example have a thickness of between 10 and 50 nanometers.
• the deposited dielectric layer 234 is then suitably shaped to expose the electrodes 21, 212, and the conductive element 24. Part of the grooves 230 is retained above the bottom of the dielectric layer 234.
• a layer of gate metal 233 has been deposited and shaped on the dielectric layers 234, and in particular in the grooves 230.
• the gate metal layer 233 is formed, for example by tungsten deposition.
• the choice of the output work of the gate metal 233 makes it possible, in a manner known per se, to adjust the threshold voltage of the transistor 1.
• the control gates 231 and 232 are obtained at the end of the shaping, typically by photolithography and etching.
• Fig. 13 is a schematic cross sectional view of an exemplary heterojunction transistor 1 according to a fifth embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally closed type.
• the transistor 1 of the fifth embodiment takes up the substrate 10 and the stack of layers 1 1 to 14 with the same thicknesses and compositions as described for the second embodiment.
• the conduction electrodes 21 1, 212, the conductive element 24 and the drain 22 are identical to those of the second embodiment.
• the control gates 231 and 232 differ from those of the second embodiment in that the gate insulators 234 are formed on the layer 14.
• the electron gas layer 15 thus remains discontinuous between the conduction electrode 21 1 and the conductive element 24 on the one hand, and between the conduction electrode 212 and the conductive element 24 on the other hand.
• Fig. 14 is a schematic cross-sectional view of an exemplary heterojunction transistor 1 according to a sixth embodiment of the invention.
• This transistor 1 is here of the gas type of holes.
• This transistor 1 is here from normally open type.
• the transistor 1 of the sixth embodiment has a structure substantially identical to that of the transistor 1 of the second embodiment.
• the transistor 1 of the sixth embodiment differs from that of the second embodiment as follows: the separation layer 12 is here a layer of N-type doped semiconductor material.
• Fig. 15 is a schematic cross-sectional view of an exemplary heterojunction transistor 1 according to a seventh embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• Transistor 1 of the seventh embodiment has a structure substantially identical to that of transistor 1 of the second embodiment.
• the transistor 1 of the third embodiment differs from that of the second embodiment as follows:
• the transistor 1 is devoid of substrate 10;
• the drain 22 is housed in a recess 1 January 1 formed in the thickness of the layer 1 1 or made on the entire rear face of the layer January 1.
• Such an embodiment is for example obtained by a method of separation of the substrate, which allows for example to use more expensive substrates to ensure the mechanical strength of the transistor 1 during the steps of its manufacturing process, and to reuse this substrate for the manufacture of subsequent transistors.
• Fig. 16 is a schematic cross-sectional view of an exemplary heterojunction transistor 1 according to an eighth embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• the transistor 1 of the eighth embodiment takes up the substrate 10 and the stack of layers with the same thicknesses and compositions as described for the layers 1 1 to 14 of the first embodiment.
• the layers 1 1 to 13 and the substrate 10 are not illustrated in this view from above.
• the transistor 1 comprises a conductive element 24 at the periphery, surrounding a control gate 23.
• the control gate 23 surrounds a central conduction electrode 21.
• the conduction electrode 21, the control gate 23 and the conductive element 24 are formed on the layer 14.
• the transistor 1 comprises another conduction electrode 22, shown in dashed lines, and positioned on the rear face at the substrate .
• the electrode 22 has an annular shape, positioned in line with the conductive element 24.
• the conduction electrode 21, the control gate 23 and the conductive element 24 have a circular outer edge.
• the conductive element 24 and the control gate 23 have a circular internal border and have an annular shape.
• the control gate 23 is configured to selectively electrically isolate and connect an inner portion and an outer portion of an electron gas layer.
• the conductive element 24 electrically connects a portion of the electron gas layer with the layer 1 January.
• a thickness of the layer 1 1 is interposed between the conductive element 24 and the conduction electrode 22.
• Such a configuration makes it possible to increase the current flow section of the conductive element 24. Since the conducting element 24 has a resistivity greater than that of the electron gas layer, it is advantageous to increase its passage section. to reduce the on-state resistance of transistor 1. There is a current passage section between the conductive element 24 and the conduction electrode 22 also greatly increased.
• the eighth embodiment can be applied to a high electron mobility transistor, a hole gas transistor, a normally open type transistor or a normally closed type transistor.
• Fig. 17 is a schematic cross-sectional view of an exemplary heterojunction transistor 1 according to a ninth embodiment of the invention.
• This transistor 1 is here of the high electron mobility type.
• This transistor 1 is here of the normally open type.
• Transistor 1 of the ninth embodiment has a structure substantially identical to that of transistor 1 of the second embodiment.
• the transistor 1 of the ninth embodiment differs from that of the second embodiment as follows: the conductive element 24 extends to the contact with the conduction electrode 22. Thus, the layer 1 1 is not interposed between the conductive element 24 and the conduction electrode 22.
• the electrode 21 is isolated from the separation layer 12, to avoid forming a short circuit between the source and the drain via the layer 12 and the element 24.

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• 2016
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• 2017
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