Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14831—Area CCD imagers
  • H01L27/1485—Frame transfer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14601—Structural or functional details thereof
  • H01L27/1464—Back illuminated imager structures

Definitions

• the present invention relates to the field of integrated image sensors and, more particularly, sensors allows ⁇ a good detection at low illumination. Presentation of the prior art
• image capture devices are known.
• the most common structure of these sensors comprises a plurality of elementary detection devices or pixels, each comprising a photodiode formed in a semiconductor substrate, associated with a charge transfer device and a charge reading circuit that has been transferred. It is generally sought to minimize the number of sensor elements by using a read circuit for several photodiodes.
• incident photons penetrate the semiconductor substrate and form electron-hole pairs in the substrate. The electrons of these pairs are then captured by the photodiode and then transferred by the charge transfer transistor to the associated readout circuit.
• the patent application US 2007/0176216 describes a structure comprising, in addition to the aforementioned elements, devices, associated with each pixel, allowing the amplification of photogenerated electrons in this pixel to improve the sensitivity of the sensors.
• CCD registers charge transfer device
• Figure 1 illustrates a pixel of an image sensor comprising a charge multiplication stage and 2A to 2E are potential curves illustrating the functioning ⁇ that pixel during different steps of the detection.
• the pixel of FIG. 1 is formed in and on a P-type substrate 10 biased to a reference voltage, for example ground.
• a photodiode consisting of a heavily doped N-type region (N +).
• the photodiode is illuminated by a light beam 13.
• an isolated transfer gate 14 controlled by a transfer signal V ⁇ .
• Next to the transfer gate 14 are formed several isolated grids for the multiplication of charges by avalanche effect.
• FIGS. 2A to 2E illustrate the potential in the substrate 10, in the plane of FIG. 1, during different stages of the image capture. In these figures, a single cycle of storage, transfer and multiplication of electrons is described. The potential illustrated in each of these figures is the potential in the substrate 10 along a line that is will call later "line of maximum potential". This line passes, deep in the substrate, by the points of strongest polarization opposite isolated grids and in the photodiode.
• the maximum polarization line passes through more or less deep points in the substrate. Note that, in the following description, we will call the grid 16 "multiplication grid" although this grid also plays a role during the initial stage of transfer.
• FIG. 2A shows the potential curve in the photodiode 12 and in the substrate 10 during an initial charge storage phase in the photodiode 12.
• the illumination of the sensor of FIG. 1 causes the storage of electrons in the region 12 and the potential of this region, initially equal to V ] _, decreases to reach a value V2 which is a function of the number of electrons stored and therefore the number of incident photons.
• V ⁇ applied to the transfer gate is zero to form a potential wall and to prevent electrons from coming out of the photo ⁇ diode 12.
• the potential ⁇ l, associated with the first multiplication grid of Charges 16 is, preferably just before the transfer step, set at a voltage V3, greater than V ] _, in anticipation of the next step.
• Vr j substantially equal to or slightly greater than V ] _, is applied ⁇ on the transfer gate 14, while the voltage ⁇ l applied to the first charge multiplication gate 16 is equal to V3 (greater than V ] _) and that the voltage ⁇ 2 applied to the second multiplication gate 18 is zero.
• the charges stored in the photodiode 12 are thus transferred into the potential well formed in the substrate 10, below the first multiplication grid 16.
• the voltage V ⁇ (transfer gate) returns to a reference potential while the voltage ⁇ 2 remains at this reference potential, for example equal to zero, which blocks the electrons in the region of the substrate 10 located under the gate 16.
• a new charge storage phase can then begin at the photodiode 12.
• a the step illustrated in Figure 2D decreases the voltage ⁇ l applied to the gate 16 to a low voltage V4. The potential of the substrate 10 located below the gate 16 is thus lowered.
• the voltages Vr j and ⁇ 2 applied, respectively, to the gates 14 and 18, are zero (reference potential).
• the voltage ⁇ 3 applied to the gate 20 is set to a voltage V5 much higher than the voltage V4, in anticipation of the next step.
• the voltage ⁇ 2 applied to the gate 18 increases rapidly to be of the order of the voltage V4, or slightly greater than V4. Since the voltage ⁇ 3 is equal to V5 (much higher than V4), the charges are transferred to the region of the substrate situated under the gate 20. The potential difference between the region located under the gate 18 ( ⁇ V4) and under the gate 20 (V5) is sufficiently high to allow the multiplication of charges by electronic avalanche effect.
• the gate 22 is biased to a zero voltage to form a potential wall and block the charges at the gate 20.
• the voltage V4 may be of the order of 1 V and the 10 V V5 voltage.
• the charge transfer step may also participate in the amplification thereof, the voltage applied to the gate 16 during this step then being adapted to produce a multiplication (high voltage).
• the steps of Figures 2D and 2E are repeated several times. For this, one carries out trans ⁇ ferts back and forth at the grids 14, 16, 18, 20 and 22, which limits the number of grids to form.
• a problem arises if it occurs a long duration with a very low level of illumination, for example in the case where the image sensor is intended to detect images in an envi ronment ⁇ dark (night images for example).
• the transfer of the charges during the step of FIG. 2B may be incomplete or be falsified.
• the signal from the detector then has very degraded performance, in particular ⁇ in terms of signal to noise ratio.
• An object of an embodiment of the present invention is to provide an image sensor allowing good detection during low illumination.
• one embodiment of the present invention provides a unit device of an image sensor include an ⁇ ing a photogenerating region and charge collection area formed in a semiconductor substrate of a first conductivity type adapted to be biased to a reference voltage, the photogeneration region being associated with a device for transferring, multiplying and isolating charges.
• the photogeneration region is surmounted by an insulated gate adapted to be biased alternately to a first voltage and to a second voltage, the insulated gate being made of a low-absorbency material.
• the transfer device comprises an insulated transfer gate adapted to be biased to a fixed voltage and in which the first voltage is greater, in absolute value, than the fixed voltage to allow the collection of charges and the second voltage is lower, in absolute value, than the fixed voltage to allow the transfer of accumulated charges.
• the device for multiplying and isolating charges is consisting of a plurality of isolated grids adapted to be polarized to fix the potential of the underlying substrate and allow the transfer of charges and the multiplication thereof by electronic avalanche effect.
• the device for transferring, multiplying and isolating charges comprises at least five isolated grids.
• the reference voltage is the mass.
• the first type of conductivity is the type P.
• the device further comprises an optical mask formed on the device for transferring, multiplying and isolating charges.
• the substrate is thinned and is intended to be illuminated by the face opposite to that on which is formed the device for transferring, multiplying and isolating charges.
• the present invention also provides an image sensor comprising a plurality of elementary devices as mentioned above. Brief description of the drawings
• FIG. 1 illustrates a sensor image with conventional charge amplification
• FIGS. 2A to 2E are potential curves illustrating the operation of the device of FIG. 1 when it is subjected to a large illumination
• FIG. 3 shows the structure of FIG. 1
• FIGS. 4A to 4C are potential curves illustrating a problem likely to be posed by this structure in the absence or at a very low level of illumination
• Fig. 5 illustrates an image sensor according to an embodiment of the present invention
• Figs. 6A and 6B are potential curves illustrating the operation of the device of Fig. 5
• Figure 7 illustrates a variant of a device according to an embodiment of the present invention.
• FIG. 3 shows the structure of FIG. 1, in a case of almost zero illumination (no light beam 13).
• the device comprises a photodiode 12 consisting of a strongly doped N-type region (N +) formed on the surface of a P-type substrate 10, an insulated transfer gate 14 formed on the surface of the substrate 10 and controlled by a signal V 1 and isolated charge multiplication gates 16, 18, 20, 22 controlled respectively by signals ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4.
• FIGS. 4A to 4C are curves of the potential in the substrate 10, along lines of maximum potential, during different stages of operation of the device of FIG. 3.
• Figure 4A illustrates the potential in the substrate 10 at a succession of stages of storage and charge transfer (the potential V L of the gate 14 varies between zero and V] _).
• V L of the gate 14 varies between zero and V] _.
• the inventors propose forming an insulated gate over a substrate and applying a potential on this gate to create a charge of space in the substrate and to collect electrons from the electron / photogenerated-hole pairs in this region.
• FIG. 5 illustrates such a device.
• the device comprises a substrate 30, for example of the P type, biased at a reference voltage (for example ground) by its rear face.
• a reference voltage for example ground
• grid 32 will be called "accumulation grid”.
• Grid 32 is not very absorbent, for example transparent, so that a light beam 34 arriving at the surface of the substrate passes through grid 32 and penetrates into substrate 30. to form electron pairs / holes.
• an insulated transfer gate 36, charge multiplication gates 38, 40, 42 and a charge isolation grid 44 are formed on the surface of the substrate 30, formed an insulated transfer gate 36, charge multiplication gates 38, 40, 42 and a charge isolation grid 44.
• the gates 36, 38, 40, 42, 44 are isolated grids and are respectively controlled by control signals V 1, ⁇ 1, ⁇ 2, ⁇ 3, ⁇ 4. Contrary to what is repre ⁇ sented in Figure 5, in an actual device, most part of the surface of each pixel is devoted to the accumulation grid 32 which represents the detection area of the dispo ⁇ operative part.
• a protective layer (not shown), or optical mask, above the transfer gate 36, the amplification grids 38, 40, 42 and the isolation gate 44 so that beams bright incidents do not generate charges in the substrate located under these grids.
• FIG. 6A is a curve of the potential in the substrate 30 of FIG. 5, along a potential line maximum, during a charge accumulation phase, before their injection into the multiplier stage.
• the voltage V applied to the transfer gate 36 is equal to a voltage V] _ and the fixed voltage V applied to the gate accumulator 32 is equal to a voltage V a] _ higher than the voltage V ] _.
• V a] _ higher than the voltage V ] _.
• the voltage V ] _ is provided sufficiently low to be less than V a 2, so that the electrons accumulate Under the gate 32.
• FIG. 6A Before the injection of the charges into the multiplier stage, the situation is that represented in FIG. 6A, the poten ⁇ tiel applied to the gate 38 being high, at a voltage V2, and the potential applied to the gate 40 being at a low level, close to zero.
• the potential V2 is greater than Vl to allow the reception of the charges during the injection.
• Figure 6B is a plot of potential in the subs ⁇ trat 30 of Figure 4, along a line of maximum potential during a charge transfer phase.
• the voltage V a applied to the accumulation gate 32 passes to a voltage V 3, less than V] _. This allows the transfer of the accumulated charges on the surface of the substrate 30 under the gate 32 to the formed potential well, on the surface of this substrate, under the first multiplication grid 38.
• the reference voltage (close to zero) applied to the gate 40 makes it possible to prevent the transferred charges from coming out of the potential well formed under the gate 38. Since the potential of the gate 32 is imposed on alternative ⁇ V] _ and V 3 avoids the aforementioned problems of increasing the surface potential of the substrate 30 under the gate 32 in a low light. This gives a complete transfer of the charges in the multiplier stage. Thus, the proposed device is effective even in case of illumination ⁇ zero or virtually zero.
• a thin N-type doped layer 46 may be formed, on the surface of the substrate 30, facing the accumulation gates 32, transfer 36, multiplication 38, 40, 42 and isolation 44.
• This thin layer 46 allows the maximum potential point of the substrate surface to be slightly removed to avoid parasitic phenomena (noises) often present at the interfaces between the gate insulator and the semiconductor substrate.
• a cycle amp ⁇ cation fillers in conventional manner. For this, we can take advantage of the electronic avalanche effect by forcing the loads back and forth under the grids 38, 40 and 42 to obtain significant amplification. The gain of the amplification is adjusted by controlling the number of round trips.
• the transfer gate 36 and the isolation gate 44 then serve as potential walls to prevent charges from coming out of the device during the amplification of the charges.
• the gates 38 and 42 are alternately polarized to potential distant to permit amplification by avalanche effect electro ⁇ nic. Note that it will also be possible to form the charge transfer and amplification device by combining more than five neighboring grids in a suitable manner.
• FIG. 7 illustrates a variant of the device of FIG. 5 in which the image sensor is illuminated by the rear face of the substrate 30.
• the device of FIG. 7 differs from that of FIG. 5 in that the substrate 30 is thinned and is illuminated by the opposite side to that on which the accumulator 32, the transfer 36, the multiplication gates 38, 40, 42 and the isolation girders 44 are formed.
• a light beam 46 reaching the substrate generates electron / hole pairs and the electrons of these pairs are collected in the potential well formed under the gate 32.
• a beam arriving through the rear face of a substrate encounters fewer obstacles and is more easily detectable than a beam arriving on the front face of the substrate.
• the operation of this device is then similar to that described in connection with FIGS. 6A and 6B.
• the reference voltage applied to the P-type substrate 30 may be different from the mass.
• the substrate 30 will be N-type doped and the voltages applied to the different grids for transfers will be of opposite sign to those presented here (the absolute values of the different voltages applied to the different isolated grids being in the same ratios as those presented in FIG. relationship with Figs. 6A and 6B).
• the devices of Figures 5 and 7 may also be used in the case of high levels of illumination. In this case, it is possible to adapt the integration time, or accumulation of charges in the accumulation zone, according to the illumination, using a suitable electronic circuit, to avoid the saturation of the pixel.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Electromagnetism (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Solid State Image Pick-Up Elements (AREA)
• Transforming Light Signals Into Electric Signals (AREA)

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• 2009
  • 2009-05-14 FR FR0953194A patent/FR2945668B1/fr not_active Expired - Fee Related
• 2010
  • 2010-05-11 WO PCT/FR2010/050920 patent/WO2010130951A1/fr active Application Filing
  • 2010-05-11 EP EP10731768A patent/EP2430660A1/de not_active Withdrawn
  • 2010-05-11 US US13/319,895 patent/US20120112247A1/en not_active Abandoned
  • 2010-05-11 JP JP2012510345A patent/JP2012527107A/ja active Pending

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