Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
  • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/45—Ohmic electrodes
  • H01L29/456—Ohmic electrodes on silicon
  • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66742—Thin film unipolar transistors
  • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78651—Silicon transistors
  • H01L29/78654—Monocrystalline silicon transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
  • H01L27/1259—Multistep manufacturing methods
  • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
  • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Definitions

• the invention relates to a method of manufacturing a field-effect transistor of planar structure, with double self-aligned grids on either side of a channel and source and drain electrodes, comprising the formation of the first gate, on a first substrate, of semiconductor-on-insulator type, the deposition, on the first gate, of a hard layer, intended to serve as an etching mask for delimiting the channel, and a pad which delimits a used space , subsequently, to form a gate cavity, the reversal and bonding of the assembly on a second substrate and the formation of the second gate in the gate cavity, photolithographic steps relating to the definition of grids, source and drain zones and the channel being all made before gluing.
• first and second grids are respectively disposed on either side of a channel, parallel to the substrate.
• a first known technique essentially uses gluing and layer transfer.
• the lower gate is first formed on a first SOI substrate. This lower grid is then used as a mask for the realization of the channel. After turning over and bonding a second substrate, an active zone is defined by photolithography and etching above the channel and the lower gate. Then, internal lateral spacers are formed in the active zone, before forming the upper grid, which they control the width.
• This manufacturing process has the following drawbacks:
• the lateral drain-channel or source-channel contact is one of the weak points of this process. Indeed, following the deoxidation of the cavity in which the drain or the source must be formed, the deposition of the gate insulator and, in the worst case, the nitride inner spacer may partially obstruct the future Drain-channel or source-channel contact zone. Gate insulator and / or nitride can therefore prevent the drain-channel or source-channel connection.
• the dimensions of the final active zone are defined by photolithography and etching, after bonding which generates mechanical deformations of the substrate, which increases the uncertainty of the alignment of the active zone with the grids.
• a suspended silicon channel is first formed between source and drain zones.
• the upper and lower grids are then defined by photolithography.
• This manufacturing process has the following drawbacks: The two grids are of different size. Indeed, the length of the lower gate is equal to the difference between the distance separating the drain and the source and twice the thickness of the gate insulator, while the length of the upper gate is determined by the mask used during the lithography of the grids.
• the two grids are not really self-aligned. Indeed, if the lithography of the grid level is strongly offset from the prior lithography of the level of the drain and the source, the cover of the grids may not be total.
• the centering of the two grids, based on the alignment of two levels of photolithography, is all the more difficult as the dimensions are smaller, especially when the gate length is less than 20 nm, for example of the order of 10 nm.
• the source and the drain are isolated from the gates only by a layer of gate insulator, without the possibility of forming spacers, which implies high parasitic capacitances between the gates and the source and between the gates and the drain.
• the grids can not be independently polarized because they form in practice a single gate structure surrounding the entire channel and not two isolated grids with respect to each other.
• the upper gate is used as a mask for the realization of the channel and the lower gate.
• Multiple spacers protect the upper gate during the etching of the channel, the channel during the etching of the lower gate and isolate the lower gate of the source and the drain.
• the two grids are of different size.
• the size of the rear grid, formed by lateral engraving, is very difficult to control. Indeed, the measurement of the length of the lower gate is only possible by a destructive control.
• US Patent 2006/022264 describes the production of a self-aligned double-gate transistor, with reversal and bonding of a first gate on a second substrate, without photolithography after bonding with source and drain zones made of semiconducting material. silicided conductor.
• the object of the invention is a method which does not have these drawbacks for the manufacture of a planar-structure double-field-effect gate transistor in which the gates are self-aligned and of the same size.
• the manufacturing process comprises, subsequent to bonding, at least partial siliciding of the layers effecting the electrical connection between the channel portion located between the self-aligned grids and the future source and drain electrodes, then the deposition of a metal to form the source and drain electrodes.
• the method comprises successively
• first lateral spacers made of insulating material, around the grid stack
• FIGS. 1 to 7, 9 to 15, 17, 18, 21, 22 and 24 to 26 illustrate, in section, the transistor at the various successive stages of a particular embodiment of the method according to the invention.
• Figures 8, 16, 19, 23 and 27 respectively show, in top view, the device according to Figures 7, 15, 18, 22 and 26.
• Figures 28 to 30 illustrate the steps of forming the upper gate, the source and the drain in an alternative embodiment with a metal top grid.
• the fabrication of the field effect transistor conventionally uses a basic substrate constituted by the formation, on a first substrate 1, constituting a mechanical support substrate, of a film 2 of material conductor on buried insulator 3.
• the first substrate constituting a mechanical support substrate, of a film 2 of material conductor on buried insulator 3.
• the film 2 consists of a thin layer (for example 50 to 200 nm thick) silicon, germanium or SiGe, so as to form a base substrate of silicon type on insulator (SOI), germanium on insulator (GeOI) or SiGe on insulator (SiGeOI).
• the buried insulator 3 is, for example, constituted by a buried oxide layer 100 to 400 nm thick. This base substrate, commercially available, is not necessarily made during the manufacture of the transistor.
• the film 2 is then preferably thinned, conventionally by oxidation (formation of an oxide layer 4, as shown in FIG. 2) and deoxidation (as represented in FIG. 3).
• oxidation formation of an oxide layer 4, as shown in FIG. 2
• deoxidation as represented in FIG. 3
• EOT equivalent oxide thickness
• FIG. 2 is preferably between 5 and 10 nm after thinning.
• An active zone 5 of the transistor is then delimited laterally (FIGS. 4 and 8) in the film 2, in a conventional manner.
• This delimitation is, for example, obtained by photolithography (deposition of a resin layer on the layer 4, formation of a mask corresponding to the active zone in the resin layer) and etching to the insulation 3 of the zones of the layer 4 and the film 2 not covered by the resin mask and elimination of the layer 4.
• the assembly is thus subdivided into 2 zones: the active zone 5 and an insulation zone 6.
• a first grid stack is then produced simultaneously on a part of each of the zones (see FIG. 8), to form a first gate 7, intended to constitute the lower gate of the transistor.
• This gate stack is formed, by deposition and etching with a hard mask, for example nitride, as illustrated in FIGS. 5 to 7, for the part of the gate stack located on the active zone 5.
• the parts of the Grid stack located on the insulation zone 6 are only shown in FIG. 8.
• the first grid 7 has substantially the shape of an I, with a central bar which completely traverses the active zone 5 and extends in the insulation zone 6. In the insulation zone, this central bar is optionally completed, at its ends, by two transverse bars to facilitate contacting, independently, on each grid.
• the stack is first constituted by successive deposition of:
• an insulating layer 8 intended to form the gate insulator
• the material constituting the hard layer 1 1 must be resistant to oxide etching.
• the insulating layer 8 may be of any suitable insulating material, for example silicon oxide (SiO 2 ), hafnium oxide (HfO 2 ) or high-K aluminum oxide ("high-K" Al 2 O 3 ).
• Other metals, such as tungsten, can also be used to form gate materials (WSi, Ti, W, WN, Ta, TaN ).
• the mask is then formed in layers 11 and 12, for example by photolithography and etching.
• This photolithography is the only critical photolithography (that is to say, to obtain patterns of very small dimensions, for example of the order of 10 nm) of the process.
• Its alignment does not pose any particular problem and can be realized in a standard way, insofar as the dimensions of the active zone 5 on which the grid must be formed are large compared to the length of the grid to be formed.
• an alignment difference of the order of 30 nm remains tolerable for a gate length of the order of 10 nm for dimensions of the active zone of the order of 300 nm.
• the layers 9 and 10 of the gate stack are etched using the hard mask, which is preserved, so as to obtain, above the gate insulator 8, a gate stack, of desired shape, having at least one hard layer at its upper part. It is then possible to implement extensions, with or without spacers (not shown).
• lateral spacers 13 made of insulating material are formed around the gate stack, for example by deposition and etching.
• the insulating material is preferably the same as that used for the hard mask, for example nitride.
• the stack of grid is then completely encapsulated in nitride (layer 11 of the mask and spacers 13) and forms the first grid 7, illustrated, in plan view, in FIG.
• the transistor channel 2a of length I 1 is then delimited by etching of the insulating layer 8 and of the layer 2, using the first gate 7 as the etching mask, that is to say its upper hard layer 11 and its lateral spacers 13.
• the same mask is used to burn, at least in part, the buried insulation 3.
• the buried insulation 3 is eliminated only on a part of its thickness. There remains therefore a thin layer not etched 3a of buried insulator, surmounted, under the mask only, a stud 3b projecting, width I and height h.
• the buried insulator is preferably etched over a height h of the order of 150 nm.
• the stud 3b is thus disposed under the channel 2a, while in the isolation zone 6, the stud 3b is arranged directly under the gate insulator.
• This pad 3b delimits a space, which will be used later to form a cavity for the encrustation of an upper grid, after elimination of the first substrate 1 and the buried insulator 3.
• the implantation and the improvement of the electrical properties of extensions can possibly be carried out at this stage, for example by SiGe epitaxy at the edge of the channel.
• source and drain zones are then delimited by deposition of a boundary layer.
• a insulator 16 preferably SiO 2
• the insulator 16 is then removed in the active zone 5, for example by photolithography and etching with a nitride stop (FIG. 14). Insulation 16 then covers the entire insulation zone 6.
• the nitride barrier layer 14 and the thin sub-layer 15 are then removed in the active zone 5 and a boundary layer 17 is deposited on the assembly, in the active and insulation zones (FIG. 14), and comes directly into contact with the side walls of the channel 2a.
• the delimiting layer 17 is made of a material having an etching selectivity (by chemical etching, plasma or chemical-mechanical polishing) that is significant with respect to the material constituting the barrier layer 14, these two materials having a significant etching selectivity by with respect to the silicon oxide constituting the insulator 16.
• the delimiting layer 17 is preferably constituted by a semiconductor material such as silicon, germanium or silicon-germanium alloys, for example amorphous silicon, polysilicon, or conductor, such as titanium nitride (TiN).
• the barrier and delimitation layers may also be constituted by nitrides of different stoichiometries, making it possible to obtain a difference in etching speed during etching, for example Si 3 N 4 SiN.
• the delimitation layer 17 is silicon, it can be formed by non-selective epitaxy or LPCVD deposit. Its thickness is, for example, of the order of 20 nm. In the advantageous case, where the delimitation layer 17 is deposited by non-selective epitaxy, the deposited silicon is monocrystalline in contact with the channel, there is then continuity of the mesh. crystalline between the channel and this portion of the delimiting layer 17, and polycrystalline or amorphous elsewhere. The deposition conditions of the epitaxial process will define whether the deposition will be amorphous or polycrystalline outside the channel contact zone. The crystallinity of layer 17, out of these monocrystalline portions, is not specifically controlled. The thickness of the boundary layer outside the single crystal zones is, ideally, between 5 and 10 nm.
• two cuvettes 18a and 18b delimited by the delimiting layer 17 have thus been formed in the active zone around the first gate 7. They delimit the future source and drain zones of the transistor.
• the assembly is then encapsulated in silicon oxide 19, and the upper part of the silicon delimiting layer 17 is removed by chemical mechanical polishing with a stop on the hard nitride layer 11 located above the first one. grid 7 in the active zone,
• the assembly is then glued on a second substrate 20 and returned.
• This bonding and reversing step is, conventionally, carried out by depositing a layer of silicon oxide (SiO 2 ) on the assembly, oxide-oxide bonding on a transfer substrate 20 provided with an oxide layer.
• the two oxide layers thus bonded constitute a buried insulating layer 21 of the second substrate 20 (FIG. 17).
• the bonding interface is preferably at least 350 nm from the upper layers 15 and 17. This relatively large distance makes it possible to prevent imperfections in the bonded surface from affecting the transistor and that this interface risks being peeled off when a later step.
• the first substrate 1 is then removed.
• the buried insulator 3 associated with the first substrate is eliminated by etching (FIGS. 18 and 19), together with the thin layer 15 of HTO of the insulating zone 6.
• the upper part of the transistor is then constituted by the stop layer 14 in the isolation zone 6 and by the delimiting layer 17 in the active zone.
• the channel 2a in the active zone 5 At the level of the gate, it is surmounted by the channel 2a in the active zone 5.
• a gate cavity (22) for the second gate is thus delimited by the boundary layer ( 17) above the first gate (7), i.e. above the channel 2a in the active area and directly above the gate insulator 8 in the isolation area.
• a layer 23 constituting the second gate insulator is then deposited at the bottom of the gate cavity 22.
• the insulating layer 23 HfO 2 for example
• Lateral internal spacers 24 are then formed in the grid cavity 22. These internal spacers 24 delimit the length of the second grid (upper grid). Their thickness is adjusted so that the upper grid has the same size as the lower grid, it could be measured before bonding and reversal.
• the gate materials consist of a layer 25 made of titanium nitride (TiN) deposited under a polysilicon layer 26.
• the grid materials of the upper grid may, for some applications, be different from the grid materials of the lower grid. In this case, the asymmetry of the gates makes it possible, for example, to adjust the threshold voltage of the transistor.
• a chemical mechanical polishing with selective stop on nitride then makes it possible to isolate the upper grids of adjacent transistors formed simultaneously.
• the small thickness of the delimiting layer 17 in the active zone with respect to the thickness of the barrier layer 14 in the isolation zone allows the delimitation layer 17 to be eliminated at the upper part of the active zone. .
• the barrier layer 14 has a thickness sufficient to not be completely eliminated during polishing.
• the thinned-out barrier layer 14 covers the insulation zone, whereas the encapsulation oxide 19 filling the wells 18a and 18b is flush in the zone. active.
• the remaining portions of the boundary layer 17 constitute a vertical partition wall between the active and insulating areas and encapsulate the lower and upper grids.
• the source and the drain are then made in the source and drain zones delimited by the cups 18a and 18b.
• the oxide 19 filling the wells 18a and 18b delimiting the source and drain zones is etched, at least in part (FIG 24), while the zone 18 insulation remains protected by the barrier layer 14 and the vertical partition walls constituted by the boundary layer 17 of amorphous silicon or polysilicon.
• the engraving must be deep enough to discover the channel 2a.
• the portions of the delimiting layer 17 discovered during the etching of the silicon oxide 19 are silicided.
• This is particularly the case of the parts in contact with the upper gate, the channel 2a and at least a portion of the lower gate.
• the upper gate comprises visible polysilicum as gate material (layer 26), this is simultaneously silicided. It is important to emphasize that the silicide layer is located on the flanks of the canal. In some embodiments, the silicide layer is located under all or part of the spacers (24, 13).
• platinum silicide will penetrate under the spacers (24, 13) themselves of length equivalent to that of the grid, c ' that is, of the order of 10 nm.
• Source and drain materials are then deposited on the assembly.
• they consist of a sublayer 27 of titanium nitride (TiN), on which is deposited a layer 28, which is thicker, made of tungsten (W) or of a tungsten-silicon alloy (WSi), in the case where the source and the drain are metallic.
• the delimiting layer 17 having been preferentially deposited to ensure the crystallographic continuity with the channel on its portion in contact with the channel and to form a continuous film in each source and drain zone, it follows that this configuration , particularly advantageous, ensures good electrical contact between the future source and drain electrodes and the channel. Indeed there is still continuity of the delineation mark 17 newly silicide with the channel 2a and at a single and there is no insulating interface between the channel 2a, and the source electrodes and drain. Under these conditions, the access resistance is optimized.
• a chemical-mechanical polishing with a stop on nitride then makes it possible to eliminate the source and drain materials in the isolation zone (on the stop 14) and on the upper gate in the active area, thus separating the source of the drain. Reversals of ⁇ contact grid and source / drain are then carried out in conventional manner.
• An additional photolithography may optionally be used to form independent contacts on the lower and upper grids, so as to allow independent control of the two grids.
• the upper grid may be metallic.
• the upper grid, the source and the drain can be simultaneously filled with the same materials.
• the process is then unchanged until the step illustrated in Figure 20.
• the polysilicon (layer 17) is silicided and metal layers 27 (TiN) and 28 (W or WSi) constituting the gate materials , source and drain are successively deposited on the set ( Figure 29).
• Chemical-mechanical polishing with a nitride stop separates the gate, the drain and the source as shown in FIG.
• the buried insulator 3 can be completely removed except for the pads located under the grid 7.
• the stop layer 14 is preferably a 10nm thick nitride layer Si 3 N 4 and the boundary layer 17 a 20nm thick layer of SiN.
• the boundary layer 17 made of SiN is etched on the uncovered side walls of the cuvettes, thus exposing the channel 2a.
• the source and the drain may be made by epitaxial silicon from the channel 2a.
• the first gate (7) formed on a semiconductor-on-insulator substrate, is surmounted by a hard layer (1 1) intended to serve as an etching mask for delimiting the channel (2a) and a pin (3b) which delimits a space used later to form a grid cavity (22).
• the second gate is formed in the gate cavity (22).
• the drain and source zones are delimited before reversal and bonding by a delimiting layer (17), preferably amorphous silicon or polysilicon.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Computer Hardware Design (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Thin Film Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=36940482

Family Applications (1)

Country Status (4)

Families Citing this family (10)

Family Cites Families (10)

• 2006
  • 2006-03-28 FR FR0602682A patent/FR2899381B1/fr not_active Expired - Fee Related
• 2007
  • 2007-03-26 US US12/224,624 patent/US7709332B2/en not_active Expired - Fee Related
  • 2007-03-26 WO PCT/FR2007/000520 patent/WO2007110507A2/fr active Application Filing
  • 2007-03-26 EP EP07731203A patent/EP1999786A2/de not_active Withdrawn

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events