EP1692792A1 - Schaltungsanordnung und verfahren zur taktsynchronisation - Google Patents
Schaltungsanordnung und verfahren zur taktsynchronisationInfo
- Publication number
- EP1692792A1 EP1692792A1 EP04804601A EP04804601A EP1692792A1 EP 1692792 A1 EP1692792 A1 EP 1692792A1 EP 04804601 A EP04804601 A EP 04804601A EP 04804601 A EP04804601 A EP 04804601A EP 1692792 A1 EP1692792 A1 EP 1692792A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- unit
- signal
- circuit arrangement
- channel
- network unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/493—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
Definitions
- Telecommunication devices such as media gateways
- a packet-oriented data traffic network to a network whose voice and data transmission is based on a time division multiplex TDM by means of gateway devices.
- Voice and / or data transmission between the networks is determined by the synchronicity of the two networks.
- a network gateway unit NUE is shown schematically in FIG.
- This network transition unit NUE is divided, for example, into a first network unit NTDM whose data transmission is based on a time division multiplex operation and a second network unit NP is a packet-oriented network unit and a system control unit SS controlling the respective firmware of the first and second network units NTDM, NP.
- the time division multiplex network unit NTDM is divided into a large number of interface units S1, ..., Sn.
- An interface unit Sn has, inter alia, a clock recovery unit CR, a control register KR, a firmware module FM, a clock selector T and bus driver BT.
- the clock recovery unit CR is supplied with primary digital carrier signals PDCl, ..., n.
- FIG. 2 shows a block diagram of a data, alarm and clock recovery unit FALC which can be used as a clock recovery unit CR in the network transition unit NUE.
- the clock signal having a clock frequency is obtained from the primary digital carrier PDCn signals present on the input side by a digital clock recovery module CRM in each case and by a subsequent one Filter module YES, for example, cleared of a route jitter.
- the interface unit Sn is usually designed in such a way that only one clock signal, which can also be referred to as a reference clock signal, is selected by the clock recovery unit CR from the data stream.
- This reference clock signal RCLK is transmitted redundantly to a packet concentrator PHUB in the second unit NP via a first bus connection REFBUS and via a second redundant connection to a clock generating unit T having a phase locked loop circuit unit PLL.
- the extracted reference clock signal RCLK (n) is generated by a selection logic on the respective interface unit
- a bus driver BT preselected and forwarded by a bus driver BT.
- the BT bus driver works in open collector mode by only applying the low potential of the digital channel signal to the bus.
- a higher-level system control unit SS ensures that only one bus driver BT is active in the interface units S1, ..., Sn at the same time. The reason for this is the need for real-time transmission of the extracted clock or reference clock signals in an unrestricted bandwidth.
- the packet-oriented network unit NP has the packet concentrator PHUB, among other things. a firmware module FWM and a clock generation unit T formed with a phase-locked loop unit PLL.
- the firmware modules FWM of the network units NTDM and NP are controlled by a system controller SS of the gateway unit NUE.
- a disadvantage of the known network gateway unit NUE lies in the high outlay involved in adapting the firmware when changes occur with regard to synchronization in the first or second network unit.
- the invention is based on the object of specifying a further circuit arrangement and a method for clock synchronization.
- the invention has the advantage that there is greater flexibility with changes in the respective network or with expansion measures of the networks.
- the invention has the advantage that an independent transmission of clock signals from a plurality of clock recovery units to a first connection takes place without the involvement of a central control unit synchronizing the first and second network units.
- the invention has the advantage that a coordinated pulse distance and pulse width coding enables simultaneous, collision-free real-time transmission of several plesochronous clock signals on a common bus signal at the same time without restriction of the bandwidth.
- the invention has the advantage that the firmware for controlling the interface unit and synchronization of the interface unit in the first network unit with the second network unit are no longer required.
- FIG. 1 shows a block diagram for clock synchronization
- FIG. 2 shows a block diagram of a clock recovery unit
- FIG. 3 shows a block diagram of a further circuit arrangement for clock synchronization
- FIG. 4 shows pulse diagrams
- FIG. 5 shows an embodiment of a bus signal PWDC
- FIG. 6 shows pulse diagrams for forming a safety margin between the clock signals different Channels
- Figure 7 display of restricted areas
- FIG. 8 block diagram of an N-channel decoder, FIG. 9 associated pulse diagram, FIG. 10 an associated mask structure,
- FIG. 11 shows a pulse interval algorithm for a 3-channel and FIG. 12 for a 4-channel bus signal.
- FIG. 3 shows a schematic structure of a circuit arrangement for clock synchronization.
- This circuit arrangement of a gateway unit NUE is formed from a first network unit NTDM and a second network unit NP.
- the first network unit is subdivided into one or more bus signal supply units CH1, ..., CHn.
- the second network unit NP has a network unit system control NPSS and a packet concentrator PHUB, a firmware FWM, a decoding unit DE with a decoder control unit DS and a clock generation unit T, for example with a phase-locked loop circuit unit PLL, being arranged in the packet concentrator PHUB is.
- the bus signal supply unit CH1, ..., CHn can preferably be implemented in a hardware module and can be configured by the operator to suit the nature of the network environment. Redundant circuit units and associated connection paths are not shown.
- the corresponding reference clock signals RCLK are recovered from the data signals DSE1,..., DSN on the input side at the bus signal supply units CH1,..., CHn in the clock recovery unit CR and each to a separately operating channel encoder KK1,..., KK4 forwarded. These reference clock signals can also be referred to as clock sources.
- a reference frequency f (REF) is generated in the channel encoder from the respective reference clock signal RCLKi present on the input side by frequency division.
- the generated reference frequency f (REF) is encoded with the aid of the reference clock signal RCLK to form a channel signal KS.
- a bus signal PWDC is formed from the individual channel signals KS ⁇ , ..., KS n via a sum signal formation unit SB and passed on to a bus driver BT.
- a bus signal PWDC is forwarded to the decoding unit DE of the second network unit NP via the first connection REFBUS.
- This circuit arrangement according to FIG. 3 has the advantage that there is the possibility here of preselecting all reference clock signals RCLKl, ..., n from a single clock recovery unit CR or individual reference clock signals from the different bus signal supply units
- CHl Generate CHl, ..., CHn and transfer them to the second network unit NP.
- the operator can use configuration to select DSEn data signals with a suitable clock quality.
- a selection of a reference clock signal RCLKn is carried out in the second network unit NP for synchronization according to a priority list which can be defined in the network unit system controller NPSS of the second network unit NP.
- the decoder control unit DS is used to switch to a different, possibly also higher priority clock quality without the involvement of the circuit units in the first network unit NTDM in connection with the network unit system control NPSS the second network unit NP carried out without delay.
- the network unit system control NPSS in the second network unit NP is immediately notified by the decoder DE of faults, such as a failure of a reference clock signal RCLKl, ..., RCLKn.
- the failed reference clock source RCLKl, ..., RCLKn is assigned in the network unit system control NPSS based on the stored configuration data.
- the advantage of this circuit arrangement and the associated method according to FIG. 3 is that the firmware module in the first network unit NTDN and a synchronization of the selection processes in the interface units are dispensed with. Another advantage is that further reference clock signals RCLKn can be selected at a later point in time without having to redesign the first network unit NTDM and to interrupt the bus operation between the network elements. This brings with it increased flexibility for the operator, so that changes in his network environment or expansion measures of his networks can be carried out at any time.
- bus signal PWDC in the bus signal preparation unit CHn is described below.
- the individual channel signals KSi, KSj are generated directly from the recovered reference clock signals RCLK by frequency reduction and coding, by generating a number of pulses corresponding to the total number of channels per channel with the periodicity of the specified reference frequency f (REF), and the pulses being fixed per channel
- Pulse distances di, dj can be assigned. These pulse distances can be equidistant distances or freely selected distances.
- the pulse intervals are also referred to as distance parameters. 5, the equidistant pulse intervals of the individual channels KSi, KSj are designed differently.
- Different pulse widths are formed within the individual channels to identify the phase distance from the reference source (rising edge of the reference frequency f (REFx).
- the pulse widths can be designed, for example, with a linear gradation. It is advantageous if the pulse widths of the pulses are increasingly formed in the pulse sequences.
- the defined pulse distances and pulse widths provide a clear assignment of the channels KS1, ..., KSn in the bus signal PWDC.
- the pulse width of the pulse PW ⁇ , ..., PW ) c is based on a quantization of the bus signal PWDC.
- the quantization of the PWDC bus signal is determined by the pulse width of the RCLK reference clock signals.
- a phase reference of the respective reference frequency f (REFx) through the leading edge of the first pulse of the channel signal KSx (reference source) enables channel selection in the decoder DE of the second network unit NP.
- the pulses of the channel signals KS1, ..., KSn are logically OR-linked to one another in the bus signal PWDC in negative logic (low-active), see FIG. 5.
- the distance parameters di, ..., dj within the individual channels are so dimension that there is still a sufficient safety distance S between the pulses of the channel signals KSI, ..., KSn, as shown in FIG. 6, between the individual pulses.
- each individual pulse in the channel signal KSI, ..., KSn has a fixed phase reference due to its predefined ned pulse width PW1, ..., PWn to its reference source.
- the PLL can thus work synchronously in the clock generation unit T despite a collision-related change in the phase position of the selected pulse sequence.
- the PLL can use the control logic DS in the decoder DE to access a large number of the redundant pulses in the channel signal and, based on the defined pulse width, carry out a phase correction corresponding to the channel-specific distance parameter in order to make a seamless transition.
- the rising edge of the first pulse with the pulse width PW1 in the channels K1, K2, K3 is arranged in a starting position (phase 0).
- the phase position is specified in phase units in accordance with the quantization q of the reference clock signal RCLK.
- q ⁇ lns and corresponds to half a period length of the 8192kHz
- a blocking area SBR ensures a sufficient safety distance between the individual pulses below the channel signals with the aim of detecting a collision with the pulse sequence selected for the clock generation unit in good time and triggering a change using the control logic to an undisturbed pulse sequence in a new phase position in the channel.
- the distance parameters di, d 2 , d 3, as also shown in FIG. 6, which can also be referred to as pulse intervals or distance parameters, are selected with a view to maintaining a possible reference clock signal by taking into account the blocking areas SBR of all channels involved.
- the resulting regulation for a scheme of a series of pulses with blocking areas SBR can be determined by the following algorithm (see Fig. 11, 12):
- n is a factor for the blocking area SBR, which ensures a sufficient safety distance between the pulses of the bus signal PWDC.
- the factor n has the phase unit q.
- n is varied in order to obtain a sufficient safety distance S, as shown in FIG. 6.
- the algorithm is illustrated below in a pulse diagram using the 3-channel system in FIG. 7.
- PW 3 the maximum pulse width
- PW 3 the maximum pulse width
- the blocking range SBR ⁇ n * q is related to the rising edge of the subsequent pulses.
- the blocking area SBR of the second pulse PW2 of the second channel K2 begins at 23 * q, so that there is no gap between the blocking areas. Only before the last blocking area around the rising edge of the third pulse PW3 in the third channel K3 is there a gap of 28 * q due to the equidistant pulse spacing (not shown in FIG. 7).
- this value in the -channel system is reduced to 32 kHz, see Fig. 12.
- the equidistant pulse spacing can be abandoned to counteract excessive limitation of the achievable reference frequency.
- FIGS. 3 and 8 An exemplary embodiment for coding and decoding the bus signal PWDC is shown in FIGS. 3 and 8 and in the pulse diagrams 9, 10 belonging to FIG. 8.
- the channel signals KSI, KS2, ..., KSn are generated in the code part KK of the bus preparation unit CH1, ... CHn with the aid of binary synchronous counters, which are clocked directly by the reference clock signals RCLK.
- the distance and pulse width parameters for each channel are defined separately by configuration data and generated using combinatorial networks. Only the reference clock signals RCLKn intended for this purpose are enabled by the clock recovery unit CR and forwarded to the bait KK.
- Enabled reference clock signals RCLKn are switched off in good time in the event of a loss of quality by the clock recovery unit CR due to an alarm module integrated in it. After combining the channel signals KSI, ..., KSn, the sum signal is passed via tristate bus drivers and transferred to the REFBUS as a PWDC bus signal.
- the mode of operation of a decoder DE in the second network unit NP is explained on the basis of a basic block diagram in FIG. 8.
- the DE decoder is among others divided into three function blocks KSY, KSK and MST. These function blocks are a channel synchronizer KSY, a channel selector KSK and a mask control MST. All function blocks are connected to the control unit DS. Depending on the number of channels, three independently operating channel separators KSP1, ..., KSPn are arranged in the channel synchronizer KSY.
- the channel signals are filtered out of the bus signal with the aid of a digital control loop in a channel separator KSP in the function block channel synchronizer KSY. For this, pulse width filters PWF or channel-specific are used for the correct selection and for keeping the synchronism in the channel synronizer
- Pulse distance filter PDF used. All of these functions are implemented as a mask function, so that a real-time transmission of the reference signals to the clock generation unit T is made possible in the decoder in an unrestricted bandwidth.
- the pulse diagram in FIG. 9 shows in the first line the signal sequence transmitted on the bus. In the following im- The output signals of the channel separators are shown in pulse diagrams. Since the channel signals are not exactly synchronized with each other, the synchronization requires three independent control loops for the three channels.
- Switching between the simultaneously available reference clocks decoded in the channel synchronizer KSY is carried out on the basis of a priority list stored in the control unit DS in the channel selector module KSK. This enables a quick hardware-controlled reaction in the event of a fault.
- the pulse train PW1, PW2, PW3 of a channel signal Kn selected in the channel selector module KSY receives a synchronously carried mask in the mask control block MST, whereby only one collision-free pulse is forwarded to the PLL per reference clock period f (REF).
- this mask is adapted to the pulse width gradation of the channel signal, the mask being subdivided into at least two areas, the passband DLB and the control area KLB.
- the pass band DLB is enabled with priority after pulse width gradation if several collision-free pulses have been found in the channel signal. The highest priority is assigned to the narrowest pulse, because it carries the phase position of the source of supply immediately.
- the control area KLB is the outer part of the mask and is responsible for collision prediction. If an external pulse runs into the control area KLB from any side, the pass-through area DLB of the mask concerned is then blocked and the next collision-free mask is simultaneously activated.
- the SBR 2 * q security area
- the digital control in the channel synchronizer works with an internal quantization of one UI, so that in addition to the quantization jitter, a UI remains reserved for the residual jitter on the channel signal in the pass band.
- the quantization of the pulse width measurement or the collision detection for the control area can be carried out with the double sampling rate of 0.5UI using both switching edges of the system clock, which increases the safety and the dynamics of the control.
- the masks are locked and unlocked in different phase positions within a selected reference clock path with the aid of a phase compensation circuit.
- phase compensation is carried out here with every mask change. In this way, the pulses selected for synchronization always meet in the same phase position from the perspective of the PLL.
- the pulse width is also regenerated after masking by digitally setting a pulse duty factor of 1: 1.
- the pulses of the reference clock signals are forwarded to the PLL without intermediate processing, i.e. in real time.
- the masks are only used to hide the redundant pulses within a channel.
- All functions of the mask control can be carried out in hardware in order to achieve optimal dynamics for the control.
- Individual mask control functions can also be outsourced to the firmware module FWM of the packet concentrator PHUB using appropriate software. The resulting longer reaction time can be caused by a possible existing holdover function in the phase-locked loop circuit PLL can be bridged.
- the channel selector module KSK can also be integrated into the module for mask control MST by correspondingly activating the pass-through masks. Furthermore, the formation of the mask areas, control area and pass area, can be directly linked to the digital control loop of the channel synchronizer.
- the phase compensation circuit can be implemented in the PLL feedback loop in a common hardware embodiment.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10357477A DE10357477B4 (de) | 2003-12-09 | 2003-12-09 | Schaltungsanordnung und Verfahren zur Taktsynchronisation |
PCT/EP2004/053154 WO2005060133A1 (de) | 2003-12-09 | 2004-11-29 | Schaltungsanordnung und verfahren zur taktsynchronisation |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1692792A1 true EP1692792A1 (de) | 2006-08-23 |
Family
ID=34672514
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04804601A Withdrawn EP1692792A1 (de) | 2003-12-09 | 2004-11-29 | Schaltungsanordnung und verfahren zur taktsynchronisation |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070116059A1 (de) |
EP (1) | EP1692792A1 (de) |
DE (1) | DE10357477B4 (de) |
WO (1) | WO2005060133A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7653092B2 (en) * | 2005-09-28 | 2010-01-26 | Electronics And Telecommunications Research Institute | Time-division multiplexing/demultiplexing system and method |
US8923341B2 (en) * | 2010-01-12 | 2014-12-30 | Vitesse Semiconductor Corporation | Method for switching master/slave timing in a 1000BASE-T link without traffic disruption |
US8839051B1 (en) * | 2011-02-25 | 2014-09-16 | Sk Hynix Memory Solutions Inc. | Advance clocking scheme for ECC in storage |
CN105320573B (zh) * | 2014-07-28 | 2019-06-14 | 群联电子股份有限公司 | 解码方法、存储器存储装置及存储器控制电路单元 |
US20160139933A1 (en) * | 2014-11-18 | 2016-05-19 | Qualcomm Incorporated | Providing loop-invariant value prediction using a predicted values table, and related apparatuses, methods, and computer-readable media |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02177739A (ja) * | 1988-12-28 | 1990-07-10 | Hitachi Ltd | デイジタル伝送方式 |
US5572554A (en) * | 1994-07-29 | 1996-11-05 | Loral Corporation | Synchronizer and method therefor |
KR0177731B1 (ko) * | 1994-09-15 | 1999-05-15 | 정장호 | 망동기용 디지탈 위상동기루프 제어방법 |
NL9401525A (nl) * | 1994-09-21 | 1996-05-01 | Nederland Ptt | Clock recovery voor ATM ontvanger. |
CA2184013A1 (en) * | 1996-08-23 | 1998-02-24 | Mauricio Peres | Hitless clock recovery in atm networks |
US5928346A (en) * | 1996-09-11 | 1999-07-27 | Hewlett-Packard Company | Method for enhanced peripheral component interconnect bus split data transfer |
DE19647093A1 (de) * | 1996-11-14 | 1998-05-28 | Bosch Gmbh Robert | Verfahren zur Aktualisierung von Zeitmarken in einem digitalen Datenstrom und Remultiplexer |
US6262998B1 (en) * | 1997-12-24 | 2001-07-17 | Nortel Networks Limited | Parallel data bus integrated clocking and control |
KR100490010B1 (ko) * | 2000-12-26 | 2005-05-17 | 엘지전자 주식회사 | 브이오디에스엘 게이트웨이의 음성 트래픽 전달 장치 |
US20030084277A1 (en) * | 2001-07-06 | 2003-05-01 | Dennis Przywara | User configurable audio CODEC with hot swappable audio/data communications gateway having audio streaming capability over a network |
GB0205350D0 (en) * | 2002-03-07 | 2002-04-24 | Zarlink Semiconductor Inc | Clock synchronisation over a packet network using SRTS without a common network clock |
-
2003
- 2003-12-09 DE DE10357477A patent/DE10357477B4/de not_active Expired - Fee Related
-
2004
- 2004-11-29 EP EP04804601A patent/EP1692792A1/de not_active Withdrawn
- 2004-11-29 US US10/582,150 patent/US20070116059A1/en not_active Abandoned
- 2004-11-29 WO PCT/EP2004/053154 patent/WO2005060133A1/de not_active Application Discontinuation
Non-Patent Citations (1)
Title |
---|
See references of WO2005060133A1 * |
Also Published As
Publication number | Publication date |
---|---|
DE10357477A1 (de) | 2005-07-14 |
WO2005060133A1 (de) | 2005-06-30 |
DE10357477B4 (de) | 2008-11-06 |
US20070116059A1 (en) | 2007-05-24 |
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