EP1449110A2 - Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung - Google Patents
Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnungInfo
- Publication number
- EP1449110A2 EP1449110A2 EP02798255A EP02798255A EP1449110A2 EP 1449110 A2 EP1449110 A2 EP 1449110A2 EP 02798255 A EP02798255 A EP 02798255A EP 02798255 A EP02798255 A EP 02798255A EP 1449110 A2 EP1449110 A2 EP 1449110A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- processor
- message
- processor unit
- distance
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Definitions
- the invention relates to a method for determining a / distance from processor units to at least one reference position in a processor arrangement and a processor arrangement.
- the processors Before using the processor arrangement, however, the processors must be organized so that the local position of the individual processors within the processor arrangement can be determined and so that the processors within the processor arrangement can be addressed individually.
- the organization should be feasible even in the event of errors occurring during the production of the processor arrangement or in the event of later failures of one or more processors or one or more connections between the processors.
- processor arrangement can be seen in a pixel arrangement, with each pixel of the pixel arrangement being assigned a processor which can control the pixel.
- the pixel can be configured as an imaging element or also as a sensor element, so that the pixel arrangement can be configured as a display unit or as a sensor field.
- a pixel arrangement with a large number of pixels in particular with a large-area dot matrix display unit or a large-area sensor field, considerable problems often occur.
- Such a pixel arrangement has, for example, in the case that it is set up as a so-called "electronic newspaper", several million pixels per page, that is, pixels.
- a pixel arrangement is understood to mean a homogeneous pixel matrix which is controlled or addressed from the edges thereof.
- a display matrix or a sensor matrix that is to say generally such a matrix
- Pixel arrangement for example, has active non-linear selection devices such as thin film transistors (TFTs) in liquid crystal display units (Liquid Crystal Displays, LCDs), which are limited in size or dimension by the properties of the thin film transistors and by the parasitic resistances of the data lines, which are used to transmit the signals from and to the individual pixels.
- TFTs thin film transistors
- LCDs liquid crystal display units
- the thin film transistors must have a current ratio of 10 5 to 10 ⁇ between the current which flows when switched on (I 0 n) and the current which flows when switched off (I 0 ff). High electrical resistances of the very thin and very long ones
- Data lines in such a pixel arrangement and a low current when the device is switched on limit the access time to individual rows or columns of the pixels in the pixel arrangement which are usually arranged in a matrix. This leads to a very slow electrical charging of the individual pixel elements. Furthermore, an excessively high current when the pixel arrangement is switched off when the matrix-shaped pixel arrangement is scanned row by row or column by column leads to a charge loss of electrical charges in the pixel capacitors, if these are not currently selected. For this reason, a control cycle, that is to say a time interval between which the individual pixel elements in the pixel arrangement are controlled, must not become too long.
- liquid crystal flat screens Furthermore, the manufacturing process of liquid crystal flat screens is extremely complex and prone to failure.
- the invention is based on the problem of specifying a method for determining a distance from processors to at least one reference position in a processor arrangement and a processor arrangement in which or at least some of the above-mentioned problems of the prior art are reduced ,
- the problem is solved by the method and by the pixel arrangement with the features according to the independent patent claims.
- processor units for at least one reference position in a processor arrangement with a plurality of processor units each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface.
- the processor units exchange electronic messages with one another, in particular between processor units which are immediately adjacent to one another.
- a first message is generated by a first processor unit, which is located at the at least one reference position.
- the first message contains first distance information, which contains the distance of the first processor unit or the distance of a second processor unit receiving the first message from the reference position.
- the first message is transmitted from the first processor unit to the second processor unit.
- the distance of the second processor unit from the reference position is determined or stored.
- a second message is generated by the second processor unit, which contains a second distance information which contains the distance of the second processor unit or the distance of a third processor unit receiving the second message from the reference position.
- the second message is transmitted from the second processor unit to the third processor unit.
- the respective messages are preferably always transmitted via the bidirectional communication interface of the respective processor units which are immediately adjacent to one another.
- the distance of the third processor unit from the reference position is determined or stored.
- the storage is preferably carried out in each case locally in a local memory which is assigned to a respective processor unit. The method steps described above are carried out iteratively for all processor units in the pixel arrangement.
- the reference position can in principle be arbitrary, preferably the reference position is a position at which a portal processor described below is located, which controls the processor units in the processor arrangement and initiates communication from outside the processor arrangement.
- the reference position can also be a position within the processor arrangement, in which case a processor unit is preferably arranged at the reference position and is assigned to it. In this case, the
- Reference position on the edge i.e. on the top or bottom row or the left or right column in the event that the processor units in the processor arrangement are arranged in a matrix in rows and columns.
- Information is preferably transmitted to or from the processor arrangement by means of the portal processor exclusively via at least part of the processor units located at the edge of the processor arrangement.
- Distance value "1” which indicates that the initiating processor unit is at a distance "1" from the portal processor.
- the first Processor unit transmits the distance value "1" to the second processor unit in the first message and the received distance value is incremented by a value "1” by the second processor unit.
- the incremented value "2" is now stored as an updated second distance value of the second processor unit.
- the second distance value is incremented by a value "1” and a third distance value is generated and transmitted to the third processor unit and stored there.
- the corresponding procedure is carried out in a corresponding manner for all processor units and the distance value assigned to a processor is updated after receipt of a message with distance information whenever the received distance value is smaller than the stored distance value.
- a processor arrangement has a multiplicity of processor units. Each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. To the
- distance information which indicates the distance of a processor unit sending the message or a processor unit receiving the message from the reference position (also referred to as distance value) and wherein each processor unit is set up such that from the
- the own distance to the reference position can be determined or stored.
- the pixel arrangement preferably the matrix-shaped pixel arrangement, is partitioned into certain areas, for example into image blocks, and an information processing unit, the pixel processor, is assigned to each area.
- the area can contain a pixel or a sensor or a plurality of pixels or sensors, each of which is controlled by a processor unit.
- the processors are preferably distributed in a coarser grid than the pixels or sensors themselves, which clearly corresponds to spatial subsampling. In this way, the problem of wiring and addressing via column lines and row lines in the case of a matrix-shaped pixel arrangement is alleviated, since the respective lines which the processor units connect to one another and with a pixel arrangement
- Connect control circuit can be dimensioned more generously, that is to say spatially thicker and thus subject to a lower electrical resistance.
- Each pixel group processor controls the corresponding image area independently, for example by means of a passive matrix control or an active matrix control.
- the size of the sub-display units is preferably selected in such a way that the problems described above of slow charging of the pixel elements and of the very short period of time between two drive cycles do not occur with a given selection device and a given wiring technique.
- pixel group processors can implement any routing instructions for the image information to be displayed or the sensor information to be detected, so that the image information or the sensor information in the form of electronic data transmission also about defects that occur in the display, that is to say in the display device, that is to say the pixel arrangement (for example in the event of physical destruction such as a punctual defect, holes, cracks, etc.).
- a pixel arrangement is thus provided and a method is provided with which it is possible in a very simple manner to determine the distance of a respective pixel from a reference position and thus also the local position of a pixel within the pixel arrangement. The determination is no longer based on global information, but on local information, which is exchanged in the form of messages between two adjacent processor units. In other words, the problem of distance determination is solved by
- the self-organization method thus has different distributed local uniform algorithms that exchange the respective messages via the respective bidirectional communication interface.
- the distance is determined on the basis of self-organization based on purely local information.
- a pixel includes both an imaging unit or a sound-generating unit, for example a liquid crystal screen unit or a polymer electronics display unit or generally any type of screen which has a multiplicity of pixels, or a loudspeaker which generates a sound wave, generally to understand each element generating an electromagnetic wave.
- the invention can be used in a pixel arrangement in which at least some of the pixels are designed as sensor elements, that is to say the pixel arrangement in this case consists at least partially in a sensor field.
- This could, for example, also be a screen unit with a touchpad integrated into it, which can in particular also be divided into a number of image tiles, in other words, a number of image areas, wherein a processor unit can be assigned to each image area.
- At least some of the sensors can each be set up as a sound sensor or as a pressure sensor (for example a piezo crystal sensor), alternatively as a gas sensor, as a vibration sensor, as a deformation sensor or as a tension sensor.
- each processor unit is coupled to at least one pixel, so that the pixel can be controlled by the respective processor unit assigned to it.
- the distances between processor units coupled to one another are determined. This is an important basis for routing of detailed image information to be displayed for the individual pixels used for the display of image information, of which the respective image information is displayed.
- the distance determination of the pixels also forms a basis for routing sensed sensor information from the pixel to the external interfaces to, for example, the portal processor.
- at least some of the pixels are each designed as a sensor. In this case, according to the invention, a distance determination is carried out for individual sensor pixels in a large-area sensor field.
- the pixels can each be designed as an imaging element or generally an element generating and emitting an electromagnetic wave, for example as a sound-generating and emitting element.
- a distance determination is carried out for individual imaging elements in a large-area, preferably matrix-shaped, display.
- the processor units can each be arranged in a hexagonal area, in which case each
- Processor unit each has six adjacent processor units, each via a bidirectional
- Communication interface are coupled to the processor unit.
- the pixels themselves can have a hexagonal shape.
- a very high packing density in the respective arrangement is achieved by using a hexagonal shape.
- the processor units can each be arranged in a rectangular area, in which case each processor unit has four adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.
- the pixels themselves can have a rectangular shape.
- the local positions of the processor units within the processor arrangement are determined by starting from a processor unit at an introduction point of the processor arrangement, each determining position messages which have at least one line parameter z and have a column parameter s, which contains the line number or column number of the processor unit sending the message or the line number or column number of the processor unit receiving the message within the processor arrangement, to adjacent ones
- processor units are transmitted and the following steps are carried out by the respective processor unit:
- the line parameter value z of the received message is assigned to the own line number of the processor unit
- new position ess messages are generated with new line parameters and new column parameters, which each contain the line number and column number of the processor unit sending the message or the line number and Column number of the recipient of the message
- Processor unit contains, and these are about the transmit bidirectional communication interfaces to a respective neighboring processor unit.
- Processor unit obtained position information is based. This enables a very robust procedure within the framework of the self-organization of the processor arrangement.
- the own distance value of the processor unit is changed in an iterative method if the previously stored distance value is greater than the distance value received in the respective received message increased by a predetermined value, and in the event that a processor unit has its own If the distance value changes, this generates a distance measurement message and sends it to neighboring processor units via all communication interfaces, the distance measurement message in each case containing its own distance as distance information or the distance value that the received processor unit has from the portal processor.
- the distance value can be changed by a value increased by a predetermined value compared to the own distance value, preferably by the value “1”.
- a pixel arrangement which has a multiplicity of pixels, which pixels are grouped into a multiplicity of pixel groups, and a multiplicity of processor units.
- a processor unit is assigned to a pixel group and controls the pixels of the respective pixel group.
- pixels are grouped into groups and one processor unit is responsible for the “reading” and “writing” control of the pixels in a group, namely the pixel of the group to which the processor unit is assigned ,
- the pixel arrangement preferably a matrix-shaped pixel arrangement, is partitioned into certain areas, for example image blocks, and each area is assigned an information processing unit, the pixel processor.
- the area can be one
- the processor unit preferably, the
- processors distributed in a coarser grid than the pixels or sensors themselves which clearly corresponds to a spatial subsampling.
- the problem of wiring and addressing via column lines and row lines in the case of a matrix-shaped pixel arrangement is alleviated, since the respective lines which connect the processor units to one another and to a pixel arrangement control circuit are, according to the invention, more generous, i.e. spatially thicker and thus can be dimensioned with a lower electrical resistance.
- Each pixel group processor controls the corresponding image area independently, for example by means of a passive matrix control or an active matrix control.
- the size of the sub-display units is preferably chosen such that the problems described above of the slow charging of the pixel elements and the very short time period between two Drive cycles do not occur with a given selection device and a given wiring technique.
- any routing rules for the image information to be displayed or the sensor information to be detected can be implemented in the pixel group processors, so that the image information or the sensor information in the form of electronic data transmission also about defects that occur in the display, that is to say in the display device, that is to say the pixel Arrangement (for example in the event of physical destruction such as a punctual defect, holes, cracks, etc.) can be redirected. This leads to an increased defect tolerance of the device according to the invention.
- a pixel arrangement is thus provided and a method is provided with which it is possible in a very simple manner to determine the distance of a respective pixel from a reference position and thus also the local position of a pixel within the pixel arrangement.
- the determination is no longer based on global information, but on local information, which is exchanged in the form of messages between two adjacent processor units.
- the problem of distance determination is solved by self-organization based on local message exchange between neighboring processor units.
- the self-organization method thus has different distributed local uniform algorithms that exchange the respective messages via the respective bidirectional communication interface.
- the distance is determined on the basis of self-organization based on purely local information.
- the hierarchical structure of the grouping can also be applied to the processor units.
- the processor units themselves are again divided into groups can be, which are controlled by further processor units of another hierarchy level, in which case one processor unit of a "controlling" group controls all processor units of the "controlled” group.
- a first set of processor units can be assigned to first processor groups and a second set of processor units can be assigned to second processor groups.
- the number of processor units of the first set of processor units is greater than the second set of processor units.
- the processor units of a second processor group are each coupled only to processor units of a respective first processor group assigned to them.
- Each processor unit of the first processor group is assigned to a pixel group and controls the pixels of the respective pixel group.
- processor units can be provided, which can be provided in any number of hierarchy levels and can each be grouped into groups of processor units, which in turn are assigned by a processor unit that is assigned to it , is controlled. In this case, a multitude of hierarchy levels arise, which further increases the control efficiency of the pixel arrangement.
- each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface.
- the processor units exchange electronic messages with one another, in particular between processor units which are immediately adjacent to one another.
- a generates a first message from a first processor unit, which is located at the at least one reference position.
- the first message contains first distance information, which contains the distance of the first processor unit or the distance of a second processor unit receiving the first message from the reference position.
- the first message is transmitted from the first processor unit to the second processor unit. Depending on the first distance information, the distance of the second processor unit from the
- a second message is generated by the second processor unit, which contains a second distance information which contains the distance of the second processor unit or the distance of a third processor unit receiving the second message from the reference position.
- the second message is transmitted from the second processor unit to the third processor unit.
- the respective messages are preferably always transmitted via the bidirectional communication interface of the respective processor units which are immediately adjacent to one another.
- the distance of the third processor unit from the reference position is determined or stored.
- the storage preferably takes place locally in a local memory, that of a respective one
- Processor unit is assigned. The method steps described above are carried out iteratively for all processor units in the pixel arrangement.
- the reference position can in principle be arbitrary, preferably the reference position is a position at which a portal processor described below is located, which controls the processor units in the processor arrangement and initiates communication from outside the pixel arrangement.
- the reference position can also be a position within the pixel arrangement, in which If a processor unit is preferably arranged at the reference position and assigned to it. In this case, the
- Reference position on the edge i.e. on the top or bottom row or the left or right column in the event that the processor units in the pixel arrangement are arranged in a matrix in rows and columns.
- Information is preferably transmitted to or from the pixel arrangement by means of the portal processor exclusively via at least part of the processor units located at the edge of the pixel arrangement.
- a first distance is assigned, for example the distance value "1", which indicates that the initiating processor unit is at a distance "1" from the portal processor.
- the distance value "1" from the second processor unit becomes transmitted in the first message and the received distance value is incremented by a value "1" by the second processor unit.
- the incremented value "2" is now stored as an updated second distance value of the second processor unit.
- the second distance value is incremented by a value "1" and a third
- Distance value is generated and transmitted to the third processor unit and stored there.
- the corresponding procedure is carried out in a corresponding manner for all processor units, and the distance value assigned to a processor is always after receiving a message with distance information updated when the received distance value is less than the stored distance value.
- the pixel arrangement has a multiplicity of processor units. Each processor unit is coupled to at least one processor unit adjacent to it via a bidirectional communication interface. To determine the respective distance of a processor unit of the pixel arrangement from a reference position, messages are exchanged between the respective processor units, preferably between adjacent processor units, each message containing distance information which indicates the distance between a processor unit sending the message or a processor unit receiving the message specifies the reference position (also referred to as distance value) and each processor unit is set up in such a way that the distance to the reference position can be determined or stored from the distance information of a received message.
- the reference position also referred to as distance value
- the global and direct processor control provided according to the prior art is advantageously abandoned via column and row lines.
- each processor unit is coupled to each processor unit immediately adjacent to it in such a way that it is connected to the neighboring processor units can exchange electronic messages.
- the distances between the respective pixels This is an important basis for routing of detailed image information to be displayed for the individual pixels used for the display of image information, of which the respective image information is displayed.
- the distance determination of the pixels also forms a basis for routing sensed sensor information from the pixel to the external interfaces to, for example, the portal processor.
- the pixels are each designed as a sensor.
- a distance determination is carried out for individual sensor pixels in a large-area sensor field.
- the pixels can each be designed as an imaging element.
- a distance determination is carried out for individual imaging elements in a large-area, preferably matrix-shaped, display.
- the processor units can each be arranged in a hexagonal area, in which case each
- Processor unit each has six adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.
- the pixels themselves can have a hexagonal shape.
- a very high packing density in the respective arrangement is achieved by using a hexagonal shape.
- processor units can each be arranged in a rectangular area, in which case each processor unit has four adjacent processor units, each of which is coupled to the processor unit via a bidirectional communication interface.
- the pixels themselves can have a rectangular shape.
- the local positions of the processor units within the processor arrangement are determined by starting from a processor unit at an introduction point of the processor arrangement
- Position determination messages which have at least one row parameter z and one column parameter s, which contains the row number or column number of the processor unit sending the message or the row number or column number of the processor unit receiving the message within the processor arrangement, are transmitted to adjacent processor units and the following steps are carried out by the respective processor unit:
- the own line number of the processor unit is assigned the line parameter value z of the received message
- the own distance value of the processor unit is changed in an iterative process if the previously stored distance value is greater than the distance value received in the message received, which is increased by a predetermined value, and in the event that a processor unit changes its own distance value, this generates a distance measurement message and sends it to neighboring ones via all communication interfaces
- the distance measurement message each containing the own distance as distance information or the Distance value that the received processor unit has from the portal processor.
- the distance value can be changed by a value increased by a predetermined value compared to the own distance value, preferably by the value “1”.
- the processor units and optionally additionally the pixels i.e. the elements generating and emitting an electromagnetic wave or the sensors to be applied to textile material and by means of electrically conductive couplings which are woven into the textile material, for example.
- the textile material itself can contain electrically conductive structures in order to electrically connect the processor units and / or the pixels to one another.
- the processor units and / or the pixels are preferably arranged on the crossing points within the structure of the textile material, e.g. at the crossing points of the electrically conductive warp and weft threads of a textile fabric.
- sound transmitters and sound sensors can be applied as pixels on the textile material, a garment preferably being made from the textile material. Using the sound transmitter and sound sensors as pixels, the position of the item of clothing and thus the position of a person wearing the item of clothing in a room or in a building can be determined.
- any sensors or actuators can be integrated as pixels in a textile material and preferably in a piece of clothing.
- the textile material is configured as textile concrete, in other words as reinforcement in the concrete.
- a textile concrete set up in this way can thus be provided in a simple manner with pixels set up, for example, as pressure sensors and / or as vibration sensors and / or as tension sensors and / or as deformation sensors.
- Such a textile concrete according to the invention can be installed very flexibly, in particular due to the self-organizing method for determining the position.
- the textile concrete with the pixels and the processor units can be used to detect possible dangerous conditions in the house (excessive weight load on a concrete ceiling) and to use the processors to send a corresponding warning message to a master computer electrically connected to it via a house interface.
- the textile concrete according to the invention can be used to build bridges.
- Textile concrete has the particular advantage that it is now very easy to determine dangerous vibrations or deformations of the bridge structure using the integrated pixel sensors and to transmit a corresponding warning message to a host computer.
- a road with textile concrete can be very simple with regard to the
- Road use for example the number of vehicles, etc.
- traffic control control generally for Traffic monitoring, even used for speed control, since the pixel sensors integrated in the textile concrete can be used to determine at which point and at what point in time a vehicle is driving over the corresponding area of the road, which is "monitored" by a respective sensor.
- Figure 1 is a plan view of a pixel arrangement according to a first embodiment of the invention
- Figures 2a to 2d top views and a sectional view of individual pixels that can be provided in the pixel arrangement, wherein the pixel can have a rectangular shape (Figure 2a), a triangular shape (Figure 2b) or a hexagonal shape (Figure 2c) ;
- FIG. 2d shows a sectional view through the pixels shown in FIGS. 2a to 2c;
- FIG. 3 shows a block diagram in which the pixel arrangement with the control device is shown schematically
- Figure 4 is a plan view of a processor arrangement according to the first embodiment of the invention.
- FIG. 5 shows a plan view of a processor arrangement according to a second exemplary embodiment of the invention
- FIG. 6 shows a plan view of a processor unit in hexagonal form
- FIGS. 7a and 7b a directed graph (FIG. 7a) and an undirected graph (FIG. 7b);
- Figure 8 shows a directed tree
- FIGS. 9a and 9b show a sketch of a processor arrangement, modeled as an undirected graph (FIG. 9a) and as a directed graph (FIG. 9b);
- FIG. 10 shows a sketch of different routing paths as a directed tree with an input node as the root
- FIG. 11 shows a sketch of an optimized routing tree
- FIGS. 12a to 12j show a sketch of the routing tree from FIG. 11 at different activation times
- Figures 13a to 13f a sketch of the routing tree from Figure 11 to different
- Figure 14 is a plan view of two hexagonal
- Figure 15 is a sketch of an incoherent processor unit
- FIG. 16 shows a sketch of a coherent processor unit when sending measurement coherence messages
- FIG. 17 shows a sketch of a processor unit, on the basis of which the sending of measurement position messages is explained;
- FIG. 18 shows a sketch of a processor arrangement after the position of the individual processor units has been determined within the processor arrangement;
- FIG. 19 shows a sketch of a processor unit, on the basis of which the sending of a measurement distance message is explained
- FIG. 20 shows the processor arrangement after the distance has been determined, the processor arrangement having a multiplicity of introductory processor units at the lower edge of the processor arrangement;
- FIG. 21 shows a processor arrangement after the distance has been determined, with every third
- a reference position is assigned to the processor unit in the bottom line of the processor arrangement
- FIG. 22 shows a sketch of a processor unit, on the basis of which the receiving and sending of MessOrganize messages is explained
- FIG. 23 shows a sketch of a processor unit, on the basis of which the organization sequence for sending a
- MessChannel message is shown in an even column within the processor arrangement
- FIG. 24 shows a sketch of a processor unit, on the basis of which the organization sequence for sending a
- MessChannel message is shown in an odd column within the processor arrangement
- FIG. 25 shows a sketch of a plurality of processor units on the basis of which the organization and the
- Figure 26 shows a processor arrangement after regular backward organization in the event that all
- Processor units in the bottom line of the processor arrangement can be supplied or sent with information from or to a portal processor;
- FIG. 27 shows a processor arrangement after regular backward organization has taken place in the event that information can be supplied or sent to or from a portal processor to every third processor unit in the bottom line of the processor arrangement;
- FIG. 28 shows a sketch of a processor unit, on the basis of which the reception and transmission of MessCountNodes messages is explained,
- FIG. 29 shows a sketch of a processor unit, on the basis of which the receiving and sending of MessNodesSize messages is explained,
- FIG. 30 shows the processor arrangement after the throughput of the processor units has been determined in the event that all processor units in the bottom line of the processor arrangement can be supplied with or sent to or from a portal processor;
- FIG. 31 shows the processor arrangement after the throughput of the processor units has been determined in the event that every third processor unit is in the lowest
- FIG. 32 shows a sketch of a processor unit, on the basis of which the sending of MessColDistance messages is explained
- FIG. 33 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement block token messages is explained;
- FIG. 34 shows a sketch of a processor unit, on the basis of which the reception of a measurement token message by an “uncolored” processor unit is illustrated;
- FIG. 35 shows the processor arrangement after meander channels have been determined in the processor arrangement when tokens have been issued in the event that all processor units in the bottom line of the processor arrangement have information from or to one
- Portal processor can be fed or can be sent
- FIG. 36 is a sketch of a processor unit on the basis of which the receiving and sending of MesseleteChannels
- FIG. 37 shows a sketch of a processor unit, on the basis of which the reception and transmission of MessColOrganize messages is explained;
- FIG. 38 shows the processor arrangement after completion
- FIG. 39 shows the processor arrangement after reorganization in the event that all processor units in the bottom line of the processor arrangement have information from or to one
- Portal processor can be fed or can be sent
- FIG. 40 shows a sketch of a processor unit, on the basis of which the initialization of the introductory processor unit color is explained by means of a MessColDistance message;
- FIG. 43 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement numbering messages is explained;
- FIG. 45 shows the processor arrangement after the numbering has been carried out in the event that information from or to a portal processor can or can be sent to every third processor unit in the bottom line of the processor arrangement;
- FIG. 46 shows a routing table according to an exemplary embodiment of the invention.
- FIG. 47 shows a sketch of a processor arrangement on the basis of which the routing and the representation of pixel data are explained
- FIG. 48 shows a sketch of a processor unit, on the basis of which the reception and transmission of measurement retry messages is explained;
- FIG. 49 shows a sketch of a processor arrangement with a multiplicity of processor units and a multiplicity of pixels, a group of pixels in each case being assigned to a processor unit;
- FIG. 50 shows a sketch of a 4 ⁇ 4 pixel group and its control by means of a processor unit
- Figure 51 shows an overview of the messages used.
- FIG. 1 shows a pixel arrangement 100 according to a first exemplary embodiment of the invention.
- the processor arrangement 100 is formed in accordance with a so-called “Fluidic Soap Assembly” (FSA) from Alien Technology TM described in [3].
- FSA Fluid Soap Assembly
- the processor arrangement 100 has a substrate 101 with a multiplicity of depressions 102.
- the substrate 101 is according to In this exemplary embodiment, a thin, flexible plastic film with a large number of recesses punched into it, via which a suspension with a large number of processor units 103, which are designed as computer chips 103 and have a size between 50 ⁇ m to 1000 ⁇ m, are washed into a liquid.
- the computer chips 103 are also referred to as nanoblocks.
- the size and shape of the integrated computer chips 103, which are referred to below as processor units 103 correspond to those of the depressions 102, so that the processor units 103 insert themselves into the depressions 102 automatically, that is to say in a self-regulating manner.
- the processor arrangement 100 becomes one
- Image display device designed in which the processor units are used to control the pixels.
- an electro-optical medium for example luminous, reflective, etc.
- a luminous medium is placed over the array of processor units 103 formed, to which electrical couplings are created on the basis of the corresponding processor units 103 controlling the electro-optical medium.
- Each processor unit 103 is responsible for the pixel located directly above it, that is to say drives it, or for the pixel region located above it, that is to say a pixel area with a plurality of pixels that are grouped into a pixel area.
- processor units 103 are also referred to below as pixel processors 103.
- the invention is in no way limited to imaging elements as a processor arrangement or pixel arrangement, but can also be used for a sensor array with a plurality of sensors that are electrically coupled to one another and controlled via one or more processor units 103 in each case ,
- Arrays can also be used according to the invention which contain partly imaging elements and partly sensor elements.
- the shape of the individual processor units 103 can be of any configuration, for example rectangular as shown in FIG. 2a, triangular as shown in FIG. 2a or hexagonal as shown in FIG. 2c.
- FIG. 2D shows a trapezoidal cross section through the respective processor units 103.
- the trapezoidal cross section ensures that the individual pixels insert themselves more easily and with greater probability into the depressions 102 of the pixel arrangement.
- the image display system 300 according to an embodiment of the invention is shown schematically in FIG. 3 in a block diagram.
- the imaging system 300 has a source 301 which represents the source of the information to be displayed and, according to this exemplary embodiment, a central processing unit (CPU), a graphics processor, Contains sensors or other input devices and optionally other components.
- a source 301 which represents the source of the information to be displayed and, according to this exemplary embodiment, a central processing unit (CPU), a graphics processor, Contains sensors or other input devices and optionally other components.
- CPU central processing unit
- graphics processor Contains sensors or other input devices and optionally other components.
- a display unit portal 302 which is electrically coupled to the source 301 is provided, which functions as an intermediary between the source 301 and the actual pixel arrangement 303 which is likewise coupled to the display unit portal 302 (which has the processor arrangement and the pixels ) represents.
- the display unit portal 302 is used according to the invention to generate a trigger, that is to say a trigger signal, in accordance with this exemplary embodiment a trigger message, for initializing the self-organization, and for distributing information about initiating processor units in the processor arrangement 303.
- the processor arrangement 303 has an array of uniform, so-called intelligent pixels or pixel regions, which are formed by processor units 103 and the pixels coupled to the processor units 103 and controlled by the processor units 103.
- the processor units 103 are meshed with one another, that is to say coupled to one another via bidirectional communication interfaces respectively assigned to the processor units 103.
- Processor units 103 in the pixel arrangement 303 serve as introduction nodes for feeding information from the display unit portal 302 into the processor arrangement 100 of the pixel arrangement 303.
- the respective processor - hereinafter referred to as the portal processor - of the display unit portal 302 has no information about the size and configuration of the pixel arrangement 303.
- the individual processor units 103 or the pixels coupled to the processor units 103 also have no information at the start of the method Information about their respective Orientation, ie orientation, or their local position within the processor arrangement.
- the individual pixel processors that is to say the processor units, also have no information about their own orientation and position, that is to say their local position within the processor arrangement.
- the portal processor of the display unit portal 302 triggers a self-organization of the processor arrangement, such as it is explained in more detail below.
- the processor units 103 of the pixel arrangement 303 learn their position and orientation as well as information paths for image construction, that is to say for supplying them
- This learning process takes place using messages which are exchanged between processor units in the pixel arrangement 303 which are adjacent to one another. Some of the knowledge that has been learned is given back to the outside, that is to say to the display unit portal 302, to the extent that the display unit portal 302 will need it later in order to display the image information in the correct ways and in the correct sequence of the pixel Arrangement 303 to be supplied for displaying an image to be displayed in each case.
- the type of image information must be taken into account for the image structure, that is to say for the procedure for distributing information to be displayed within the pixel arrangement 303.
- individual pixel data for representing a complete image or a differential image are transmitted to the individual pixels, that is to say more precisely to the individual pixel processors 103.
- each pixel processor 103 is individually addressed by the portal processor of the display unit portal 302. This leads to routing of the image information to the corresponding pixels, and thus to the corresponding processor units within the pixel arrangement, which is required as part of the display of image information.
- Routing routes are only determined between the portal processor of the display unit portal 302 and the individual pixel processors, that is to say the processor units of the pixel arrangement 303, but not between the pixel processors.
- the routing volume is even, ie exactly one pixel date must be transmitted to each pixel processor for each digitized image to be displayed.
- Pixel processors provided within the processor arrangement.
- the choice of routing routes within the processor arrangement is based on local information which is exchanged between the individual pixel processors using electronic messages.
- two phases are to be differentiated when using a pixel arrangement according to the invention:
- a first phase the so-called self-organization
- a second phase the so-called self-organization
- Pixel processor can receive an electronic message from the processor of the display unit portal 302.
- the image data are sent from the portal processor to the pixel processors, that is to say transmitted, as a result of which the image to be displayed is built up in the pixel arrangement 303.
- the pixel processors 103 in the event that they have a rectangular shape, preferably a square shape, on each side of the rectangle via one of the four bidirectional communication interfaces 401 per provided
- FIG. 5 shows another exemplary embodiment in which each pixel processor 103 has a hexagonal shape and six bidirectional ones per pixel processor 103
- Communication interfaces 501 also on each side, that is to say the side edge, of the respective pixel processor 103 are provided.
- each pixel processor 103 has six neighboring pixel processors 103, with which the respective pixel processor 103 is coupled via a bidirectional communication interface 501 and an electrical line 502 for the exchange of electronic messages.
- the pixel arrangement 100 thus has two types of individual components:
- Pixel processors 103 each of which is assigned up to six bidirectional communication interfaces 501 and electrical lines 502, and
- Bidirectional connections furthermore also as bidirectional communication interface 501 and electronic line 502 assigned to the respective communication interface 501, each of which couples two pixel processors 103 or one pixel processor 103 and the portal processor.
- the hexagonal pixel processor 103 can have six different orientations, as shown in FIG.
- the individual connections that is to say also the individual communication interfaces 501, have already been oriented during the self-organization phase, as will be explained in more detail below.
- the connections are numbered in accordance with this exemplary embodiment and identified with cardinal directions for better understanding, the following nomenclature being used in accordance with this exemplary embodiment: a first orientation 0 (east) (reference symbol 600), in other words an orientation to the right,
- a second orientation 1 (northeast) (reference number 601), in other words an orientation to the top right,
- a third alignment 2 (northwest) (reference symbol 602), in other words an alignment to the top left,
- a fourth orientation 3 (west) (reference number 603), in other words an orientation to the left,
- a fifth orientation 4 (south-west) (reference symbol 604), in other words an orientation towards the bottom left, and
- a sixth orientation 5 (southeast) (reference numeral 605), in other words an orientation towards the bottom right.
- the portal processor of the display unit portal 302 has electrical connections to pixel processors 103 on only one side of the pixel arrangement 100.
- this is the lower side of the pixel arrangement 100, that is to say clearly the south side, the couplings likewise by definition running over the south-west side, that is to say over the fifth alignment direction of the respective pixel processors 103.
- both the positioning and the orientation of the individual introduction points of information about the pixel processors 103 in the processor arrangement 100 and the shape and orientation of the individual pixel processors 103 in the processor arrangement 100 are basically arbitrary .
- pixel processors 103 of the bottom line of the processor arrangement in a predetermined, regular, that is to say periodic distance, that is to say every third, fifth, tenth, etc., pixel processor 103 within the bottom line of the processor arrangement.
- the portal processor knows the number of its connections to the pixel processors 103 after the manufacture of the pixel arrangement 303, in other words the number of introduction points for supplying information to pixel processors 103 within the pixel arrangement 303, it does not necessarily know the dimension and the configuration of the Pixel arrangement 303 and thus the processor arrangement, that is to say the actual shape and arrangement of the pixel processors 103 within the processor arrangement 100.
- an indication of the direction for example the south side, does not necessarily have to represent a straight line within the processor arrangement 100.
- the respective component of the pixel arrangement has failed completely. If the component is a processor unit, all connections to this processor unit must also be declared defective.
- Unstable The component has partial failures, for example a direction of a bidirectional connection between the respective processor unit only works intermittently (that is to say it has a loose contact or works methodologically incorrect, for example a processor which sends an incorrect message).
- Role whether a component does not exist due to a special shape of the pixel arrangement for example, a display unit film which has the shape of a triangle), or whether the respective component has become defective due to a manufacturing defect or due to wear.
- Each pixel processor 103 in the pixel arrangement 303 is set up in such a way that it can carry out the following actions within a time cycle:
- An electronic message can thus only be transmitted from one pixel processor 103 to a neighboring pixel processor 103 within a time cycle.
- the pixel processors 103 and the display unit portal 302 are modeled together as a directed graph and the routing paths as a directed tree.
- ⁇ : ⁇ ((x, y), (y, x)) £ V 2 x V 2 ; with x, ye Vj V 2 XV 2
- [x, y]: ⁇ (x, y), (y, x) ⁇ , for all x, y £ V.
- undirected graph with set of vertices (set of nodes) V, set of edges M and incidence mapping u.
- FIG. 7 a shows a directed graph 700 and FIG. 7 b shows an undirected graph 701.
- V, E, g be a directed graph
- V, E, g is called directed tree, if there is a we V such that
- 1, for all ve V ⁇ ⁇ w ⁇
- the second condition in the above definition 4 guarantees the uniqueness of the root, which would not otherwise exist, and prevents the existence of "superfluous" edges in the tree.
- Figure 8 shows an example of a directed tree 800 as part of the directed graph outlined in Figure 7a.
- Lemma 5 (properties of a directed tree)
- V E (v): ⁇ v ⁇ ⁇ z ⁇ V; T E (v, z) ⁇ ⁇
- w ⁇ V is an excellent knot and hot portal (knot).
- (v, E, g) be the directed graph for which the following applies: For every m ⁇ M consider new elements m ⁇ and m such that
- u (m) jg (m ⁇ ], g (m If, for all m ⁇ M.
- v, E, g a display unit graph, hereinafter also referred to as a display graph.
- FIGS. 9a and 9b A corresponding undirected graph 900 (cf. FIG. 9a) and the directional pixel arrangement graph 901 (FIG. 9b) that is equivalent thereto are shown by way of example in FIGS. 9a and 9b.
- the directed graph 901 is generally a flat graph or a graph that can be smoothed (extensions are conceivable in which this only applies to the sub-graph, which does not contain the portal node 902 if the feed lines 904 are not fed in at the edge of the pixel arrangement 100).
- the portal node 902 makes sense to mark, in addition to the portal node 902, those nodes 903 which have a direct connection to the portal node 902. As described above, these nodes are referred to as initiator nodes 903, that is to say they represent the reference positions to which the initiator pixel processors of the pixel arrangement are assigned.
- the edges from the portal node 902 to the introduction node 903 are referred to below as feed lines 904 and the edges 905 between pixel processors as network connections.
- Definition 10 (supply lines, network connections, initiator nodes)
- the amount of the initiator nodes is defined by
- each node of a pixel arrangement graph from the portal node an electronic message is to be transmitted within a time frame (within a refresh rate).
- the routing tree is not unique; in general the amount of all possible trees is unmanageable.
- (v, E, g) be a display graph with portal nodes w ⁇ V.
- the set of all permitted directed trees in (v, E, g) is defined as
- K: ⁇ KCE; (v, K, g
- FIG. 10 An exemplary permissible tree 1000 is shown in FIG. 10 with the corresponding routing routes with the portal node 1001 as the root node of the directed tree 1000. Based on Definition 10, the following terms are introduced:
- Definition 12 (supply lines, network connections)
- K net : E net ⁇ ⁇ •
- (v, E, g) be a display graph with portal nodes w ⁇ V and the set K of the permissible edge sets.
- Minimizer of the functions L and K and particularly suitable as a routing tree are known in the art.
- the problem can also be understood as a multi-criteria combinatorial optimization problem with two target functions.
- the routing tree 1000 in accordance with FIG. 10 is certainly not optimal, and specifically not in accordance with any of the above criteria.
- the tree 1100 according to FIG. 11, on the other hand, is even in 0] _ cut with O3.
- (V, E, g) be a display unit graph with portal node w.
- r:
- K ⁇ ki, ..., k r ⁇ ⁇ K (note:
- ⁇ ) is a matrix
- c p ort means capacity of the supply lines
- c ne t means capacity of the network connections
- q means maximum queue length
- ⁇ : n is called routing duration.
- ⁇ ) become with
- the extension compared to the previously considered routing trees consists primarily in the fact that ⁇ also contains a temporal component.
- the matrix entry ⁇ ij, i e ⁇ 1, ... n ⁇ j ⁇ ⁇ l, ... r ⁇ states that messages are transmitted over the edge kj in the i-th time cycle ⁇ i.
- Condition (i) ensures compliance with specified supply capacities and network capacities.
- Condition (ii) ensures the necessary causality in the network. Messages can only be forwarded from a node if they have been sent to this node beforehand (i.e. at least one time clock earlier).
- Condition (iii) takes into account space constraints in the nodes.
- the routing matrix together with the routing tree, thus specifies a routing method with an indication of the chronological sequence of the individual steps, which simultaneously supplies the network with messages.
- a (Cp ⁇ r ⁇ , Cnet 'q) routing is a tuple (K, ⁇ ) consisting of a permissible edge length
- ⁇ iy: max- ie ⁇ l, i y + 1 - l ⁇ :> 0
- a matrix entry ⁇ . • 1 means that the message is forwarded to V_ in the i th time cycle via the edge kj.
- Definition 18 (routing matrix for individual nodes)
- Routing matrices for the nodes V] _, 1 1, ..., r regarding (K, ⁇ ).
- ⁇ : ⁇ ⁇ 1 . l ⁇ l ⁇ r
- Optimal routing is understood to mean routing from the following set
- K ⁇ ki, ..., k r ⁇ e K, ⁇ ⁇ Rc port , c net , q ( ⁇ )
- Introductory node arrives and in the following time intervals is gradually forwarded to its respective target node, that is to say the target pixel processor.
- the messages to the nodes further away are fed in first, later the messages to the nodes located close to the portal node, that is to say the pixel processor.
- the small squares each symbolize an electronic message 1201, which is routed via the portal node 1202 to the initiating pixel processors 1203 in the pixel arrangement 100.
- the first two messages 1201 are fed to the introductory pixel processors 1203, that is to say the pixel processors of the pixel arrangement 100, via which the information about the pixel arrangement can be supplied to the respective pixel processors, and stored there temporarily (cf. Fig.12b).
- the first two messages have already been transmitted to first inner nodes 1204 of the pixel arrangement and two further messages 1201 have been fed to the initiating pixel processors 1203.
- a routing matrix is thus developed that defines an optimal (C ⁇ r t, c ne t, q) routing via (V, K, g
- the minimum routing duration can finally be determined from it.
- n: max dj ⁇ (v) veV port
- ⁇ is an optimal ⁇ Cp ⁇ r , c ne qj routing via (v, K, g
- n max n u u ⁇ vport
- a "sufficiently wide branch” is clearly present when the following applies to all initiating nodes: look at the branch of the initiating node, arrange the associated nodes according to the ascending path length. Then the path lengths of the nodes should only increase every c nodes by the value 1, i.e. c nodes of path length 2, c nodes of path length 3, ....
- the introductory nodes represent a constriction of the tree. At higher ones
- the topology of the network that is to say the arrangement of the pixel processors in the processor arrangement, is unknown to the central external unit, that is to say the portal processor.
- the pixel processors are meshed with each other through bidirectional connections.
- Fig. 14 shows a first pixel processor 1401 with a hexagonal shape and a second pixel processor 1402, also in a hexagonal shape.
- the first pixel processor 1401 has six bidirectional communication interfaces 1403, which is indicated by a double arrow in FIG. 14.
- the second processor unit 1402 also has six bidirectional communication interfaces 1404.
- the first processor unit 1401 and the second processor unit 1402 are via a feed line 1405, that is to say an electrically conductive connection, which of course is also an optical one
- Communication connection can be configured or coupled to one another as a radio link such that both a first message 1406 can be transmitted from the first processor unit 1401 to the second processor unit 1402 and a second message 1407 from the second processor unit 1402 to the first processor unit 1401.
- all pixel processors 1401, 1402 are fully meshed with one another via the corresponding feed lines and the bidirectional communication interfaces.
- the self-organization process thus consists of distributed uniform algorithms that transmit these electronic messages via their communication interfaces.
- the processor units 1401, 1402 learn their alignment and their level position within the processor arrangement, as well as the distance between them Processor unit to the portal processor, generally to a reference position.
- the reference position can also be the position of a processor unit, which is located at the point of introduction of the pixel arrangement.
- local routing paths between the individual processor units and the portal processor are shaped.
- the algorithms for selecting the routing routes are designed in such a way that the routing duration is kept to a minimum, while the information flow is uniform.
- the self-organization also defines the algorithm for distributing the information when using the pixel arrangement in the context of the image construction, that is to say in the context of the representation of a digitized image on the pixel arrangement. Due to the special conception of the method, the shape of the pixel arrangement and thus also the individual components that have failed are irrelevant, with which a high fault tolerance is achieved according to the invention.
- the entire method has a combination of the following sub-methods: • Uniform sub-algorithms for message processing, which are executed by the pixel processors,
- functions lying below the functions required according to the invention for example ping messages, securing the transmission by means of checksums, acknowledgment of receipt, New requests for defective messages etc. are not taken into account in the following. However, these can easily be implemented within the scope of the invention.
- each pixel processor creates a data record for each of its neighboring pixel processors on the basis of received messages, which data record the information obtained in a memory assigned to the respective processor.
- the pixel processors learn how to align them evenly.
- measurement coherence messages are sent, which contain as parameters the number of connections that the receiving connection is counterclockwise from the east, as defined above.
- Each pixel processor is set as incoherent for initialization.
- the processor unit 1500 receiving the measurement coherence message 1501 carries out the following steps:
- the east direction is determined based on the message parameter and all connection names / connection numbers are aligned accordingly. 3.
- the processor unit 1500 is set as coherent.
- Measurement coherence messages 1601, 1602, 1603, 1604, 1605, 1606 are sent out by processor unit 1500 over all connections, the parameters of which are selected such that the respective measurement coherence message 1601, 1602, 1603, 1604, 1605, 1606 receiving processor units 103 can align themselves correctly in the above manner (see FIG. 16)
- the partial method for uniform alignment is started by the portal processor transmitting the measurement coherence message (2) with the parameter value 2 to the respective introductory pixel processors via its connections.
- the partial process terminates when the last processor unit has become coherent.
- the number of times required to carry out the process corresponds to the maximum distance of a pixel processor from the portal processor. Until the last message communication "dies", one or two more clock cycles may be required.
- the pixel processors determine electronic exchanges
- the coordinate system according to this exemplary embodiment is selected such that the column numbers in the rows are alternately even or odd.
- the coordinate system can be selected very canonically in the case of an orthogonal structure of the pixel arrangement.
- the hexagonal field enables a processor to determine the positions of its neighboring pixel processors independently of the geometry of the pixel arrangement from its own position (i, j) with row i and column j.
- FIG. 17 The respective positions are shown in FIG. 17 for the processor unit 1500. As can be seen in Fig. 17, it has been agreed as a convention that the column numbers increase from west to east (left to right) and the line numbers increase from south to north (from bottom to top).
- each pixel processor For initialization, the position of each pixel processor is defined as (0.0). The process of determining location begins with each pixel processor once it has become coherent, as discussed above.
- the measurement position messages 1701, 1702, 1703, 1704, 1705, 1706 are then sent over all connections, as shown in FIG.
- measurement position messages 1701, 1702, 1703, 1704, 1705, 1706 are sent over all connections, as in FIG. 17 shown.
- the partial procedure is ended when there are no more changes in position.
- FIG. 18 shows an example of the processor arrangement 1800 with various defects, which has automatically determined the positions of the individual processors according to the procedure described above. According to this embodiment, both failed, i.e. faulty processors used as well as failed connections.
- This exemplary embodiment also serves in the further course of this description in two variants with a different number of initiating processor units for describing the further sub-methods.
- the number of clock cycles required to carry out the process is limited by the maximum distance of a pixel processor from another pixel processor in the processor arrangement. Until the last message communication "dies", one or two more clock cycles may be required. Usually, however, depending on the geometry of the processor arrangement 1800, the partial method can usually be carried out even faster.
- the local position of the respective pixel processor 1801 within the processor arrangement 1800 is plotted in the form of a value group in the pixel arrangement for each pixel processor 1801.
- the respective distance of a processor unit from the portal processor that is to say the length of the path from the pixel processor to the portal processor (see also definition 6), generally the distance of a processor unit 1801 in the processor arrangement 1800 from a predetermined one Reference position.
- the distance between each processor unit 1801 is defined as "infinite". According to this exemplary embodiment, the distance between each pixel processor and the portal processor is defined as a value that is greater than a maximum value that can be assumed as a distance within the pixel arrangement.
- the process of determining the distance is then started by the portal processor by sending MessDistance (0) messages to the processor units at the introduction points of the processor arrangement 1800.
- MessDistance (0) messages When a MessDistance message with distance parameter a is received, the following steps are carried out by the respective processor unit receiving the MessDistance message:
- step 1 If, due to step 1, there has been a change in your own distance d, then all
- the respective MessDistance message 1901, 1902, 1903, 1904, 1905, 1906 contains as parameters the distance value that the processor unit 1500 determined in the previous step.
- the partial procedure terminates when there are no more changes in distance.
- FIG. 20 and FIG. 21 show the processor arrangement 1800 according to a first exemplary embodiment and a processor arrangement 2100 according to a second exemplary embodiment, with all processor units 2001 in the bottom line 2002 of the processor arrangement in the processor arrangement 1800 according to the first exemplary embodiment.
- Arrangement 1800 are coupled to the portal processor via their southwest side 2003.
- the bottom line 2101 of the processor arrangement 2100 contains both processor units 2102 which are not coupled to the portal processor and processor units 2103 which communicate with the portal processor via their communication interfaces 2104 arranged on the south-west side are coupled. According to the second
- Exemplary embodiment is every third processor unit in the bottom line 2101 over its lying on the southwest side Communication interface connected to the portal processor.
- the number of time cycles required to carry out the process corresponds to the maximum distance one
- Processor unit from the portal processor. Again, one or two more clock cycles may be required before the last message communication "dies".
- Processor unit can also store the distance of its direct neighboring processor units from the portal processor locally for later use based on the messages received.
- the own distance value of the processor unit is changed in an iterative process if the previously stored distance value is greater than the received distance value increased by a predetermined value in the respectively received message.
- a processor unit changes its own distance value, it generates a measurement distance message and sends it to neighboring processor units via all communication interfaces, the measurement distance message each containing the own distance as distance information or the distance value that the received processor unit from the Portal processor preferably has a value increased by a predetermined value compared to its own distance value, preferably a distance value which is increased by the value "1".
- connections between the respective processor units are hereinafter referred to as channels.
- the sets of processor units with the portal processor as the root node and the channels as the edges between the respective processor units form a tree. This tree is used for the subsequent routing as described above in connection with the graph-theoretical basics.
- the channels are determined in a regular manner so that each processor unit is connected to the portal node in the shortest possible way.
- each pixel processor is 1500
- the process of organization is started across all connections by the portal processor by sending MessOrganize messages 2201, 2202, 2203, 2204, 2205, 2206, which have no parameters.
- the processor unit determines a neighboring processor unit which is at a smaller distance than it itself from the reference position, and thus preferably from the portal processor.
- the neighboring processor unit is selected and defined as the "predecessor", which is the first to have a shorter distance than the processor unit itself in the order defined in FIGS. 23 and 24.
- the connection between the processor unit and its "predecessor" becomes special excellent and called "channel”.
- the set of pixel processors with the portal processor as nodes and the channels as edges then form a tree. In the case of a regular display without errors, this procedure leads to a "zigzag pattern" when defining the channels.
- the processor that receives the Mess Channel message defines the sender as "successor". The is accordingly
- the partial process terminates after all processor units have organized themselves in this way.
- FIG. 25 shows an example of an organized processor unit 2500, the connections 2501, which are channels, being optically highlighted.
- the pixel information for example the image information to be displayed, is routed via the channels 2501.
- Fig. 26 and Fig. 27 show examples of the processor arrangement 1800 and 2100 after automatic organization, as described above.
- the number of times required to carry out the partial method for rearward-facing self-organization corresponds to the maximum distance of a pixel processor from the portal processor. In this case, one or two more clock cycles may be required until the last message communication "dies".
- the throughput of a pixel processor is of considerable importance for setting up routing tables.
- the throughput is the number of pixel information that must be processed or passed on by this processor in order to build up an image.
- a tree structure must have been organized in the processor arrangement 1800, 2100, for example by means of channels, as described above.
- the partial process is carried out by the portal processor
- the processor unit receiving the MessCountNodes message performs the following steps:
- MessCountNodes messages 2802 are again sent over all output channels of the processor unit receiving the MessCountNodes message, as shown in FIG.
- All neighboring processor units which are connected to one another via output channels are marked with a throughput with the throughput value "0".
- a MessNodesSize message 2901 is sent to the respective predecessor processor unit via the input channel.
- 29 shows for a processor unit 1500 two incoming MessNodesSize messages, a first incoming MessNodesSize message 2901 which contains the value di and a second incoming MessNodesSize message 2902 with the parameter d 2 .
- the neighboring processor unit from which the MessNodesSize message 2901, 2902 was received is with the
- the partial procedure terminates after the portal processor has received a MessNodesSize message over all connections.
- the number of time cycles required to carry out the partial method corresponds to twice the maximum distance of a pixel processor from the portal processor. In this case, one or two more clock cycles may be required until the last message communication "dies".
- FIGS. 30 and 31 show examples of the processor arrangement 1800 and 2100, respectively, after the throughputs have been determined automatically in the manner described above.
- the respective throughput value is specified in the respective pixel processors. These examples show that the throughputs of those single-processor units which have to supply the area of the processor arrangement 1800 or 2100 shaded by the respective horizontal crack 2600, 2700 are very high.
- Delivery point is loaded with tokens of a different "color”.
- the processor arrangement 1800, 2100 is divided into color regions, each of which is supplied by the portal node via an initiating processor unit.
- color is used for a clearer illustration and accordingly an area marked with the same marking is used as the "color region”.
- a token weight determines how much the distance to the portal node can be increased due to the coloring.
- the processor unit sending the token becomes the “predecessor” and the connection to it becomes the channel. Furthermore, the colored pixel, that is to say the marked process unit, “.only.” Still accepts tokens from the respective predecessor.
- Tokens are preferably sent via channels.
- the distance determination within a color region is largely identical to the general distance determination to a reference position described above.
- the color distance determines the length of the shortest path from a processor unit to the portal processor, whereby all processor units of the path must belong to the same color region.
- the color distance of each processor unit is defined as infinite and its color as undefined.
- the distance between each pixel processor and the portal processor is defined as a value which is greater than a maximum value which is assumed to be a distance within the pixel arrangement can.
- the processor unit also marks its neighboring processor units as undefined colored with an infinite color difference.
- Processor unit is marked with the color c and the color distance a.
- the own color difference d is set as the minimum of the color differences of neighbors marked in the same color plus the value 1.
- MessColDistance messages 3201, 3202, 3203, 3204, 3205, 3206 with the parameters (f, d), that is to say in other words with, are sent over all connections your own color difference d and your own color f (see Fig. 32).
- the invention uses
- MessBlockToken messages used that is, after receiving such a MessBlockToken message, no more tokens may be sent to these blocked neighboring processor units.
- the color and color difference are communicated as in the MessColDistance message.
- all neighboring processor units of a processor unit are set as unblocked.
- the processor unit receiving the MessBlockToken message performs the following steps:
- the processor unit sending the MessBlockToken message is set as blocked and marked with the color c and the color difference a.
- step 5 If the color c does not match the own color f, that is to say the color of the processor unit receiving the measurement block token message, the processing is continued with step 5 described further.
- the own color difference d is set as the minimum of the color differences of neighboring processor units marked in the same color plus the value 1.
- step 3 If there is a change in your own color difference d due to step 3, the
- a measurement block token message 3302 with the parameters (f, d) is generated and sent via the input channel, as shown in FIG. 33.
- measurement token messages are used according to the invention.
- the potential own color distance pd is set as the minimum of the color distances of neighboring processor units colored with the color f + 1.
- a measuring block token message is sent to the processor unit sending the MessToken message 3401 and the processing is ended (the spread of the tokens is therefore restricted by a relaxed distance).
- the processor unit sending the MessBlockToken message 3401 is set as blocked. Your own color is set as f and your own color difference as pd.
- the processor unit sending the measurement token message 3401 is sent a measurement channel message and the processor unit is set as organized. This defines the input channel.
- Measurement block token messages are sent over all connections with the exception of the input channel of the processor unit 1500 3402, 3403, 3404, 3405, 3406, as shown in Fig. 34, to prevent a token assignment from there.
- a MessToken message with the parameters (g, f) is sent via this output channel, i.e. the token is passed on and processing is ended.
- a MessBlockToken message is sent via the input channel because the token cannot be passed on. Since the channels cannot be optimally set when selecting the color regions due to the partial method described above, as shown in Fig. 35, these channels are deleted with MessDeleteChannels messages and set again later. To terminate the partial process, the message is provided with a parameter "sta p", the value of which is not identical to the correspondingly stored parameter in the processor unit. In this context it should be noted that the portal processor uses a different parameter "stamp" for each reorganization.
- the processor unit receiving the respective MessDeleteChannels message carries out the following steps:
- MessDeleteChannels messages 3602, 3603, 3604, 3605, 3606 are sent with the parameter “stamp” over all connections with the exception of the connection to the processor unit sending the MessDeleteChannels message, as shown in FIG. 36.
- the neighboring processor units under consideration have to be colored in the same way as the processing processor unit, and that it is not the distance but the color distance that is used as a criterion.
- connections are specifically labeled "channels”.
- the portal processor sends a MessColDistance message 4001 (see FIG. 40) with the parameters (f, 0) with different color parameters f over all connections. All neighboring processor units thus mark the portal processor with a different color.
- the portal processor sends successive measurement token messages with the parameters (g, f) with identical weight g ⁇ NQ and different color parameters f over all connections in order to color all processor units of the processor arrangement 1800, 2100.
- the partial method terminates when measurement block token messages have arrived via all connections of the pixel processor, that is to say when the processor arrangement 1800, 2100 has been completely colored.
- meandering paths 3801 are formed within the colored areas, so that the processor units are not connected to the portal processor by the shortest possible distance.
- the portal processor sends a MessDeleteChannels message, as explained above, over all connections in order to delete the channels formed.
- a MessColOrganize message is sent across all connections, creating new channels within the colored areas, which then represent the shortest connections.
- the partial process terminates after all processor units have organized themselves in this way.
- the number of times required to carry out the processes corresponds to the maximum color distance of a pixel processor from the portal processor. Until the last died
- the routing tree generated depends on the weight g, which is contained as a parameter in the respective measurement token message.
- the weight g indicates how much the color difference one
- the processor unit may be larger than the distance itself.
- the greater the weight g the better balanced the tree that will be created, but the longer the paths in this tree are.
- weight usually depends on the transport properties of the respective connections, i.e. how many messages can be sent over a connection per time cycle. The smaller this number is, the larger the weight will usually have to be.
- the numbers are then used as destination addresses for routing.
- the local information collected is transmitted from the respective processor units to the portal processor.
- the overall routing table is then created in the portal processor.
- measurement numbering messages are used to number all processor units in the pixel arrangement 1800, 2100.
- the prerequisite is that the throughput of the respective processor units has already been determined, for example in accordance with the partial method described above.
- the partial process of numbering is carried out by the portal processor by sending measurement numbering messages 4301 via the output channels of the portal processor
- the respective measurement numbering message 4302 of the parameters 1, 1 + di, 1 + di + d, ... is also transmitted as a message parameter.
- the Processor unit receiving MessNumbering message 4301 performed the following steps:
- the processor unit's own number is set to the value n, which corresponds to the value of the received measurement numbering message
- An additional measurement numbering message 4302 generated by the processor unit is generated over all output channels of the processor unit and with the
- di, d 2 , ... are the throughputs of the corresponding neighboring processor units.
- the partial process terminates when the last processor has been numbered by the last processor unit.
- the number of time cycles required to carry out the partial method corresponds to the maximum distance of a processor unit via channels from the portal processor. Until the last message communication "dies", one or two more clock cycles may also be required in this partial method.
- FIG. 44 and 45 show the pixel arrangements 1800 (FIG. 44) and 2100 (FIG. 45) after the individual processor units have been numbered within the respective pixel arrangement.
- the number of a processor unit can simply be used as an address for routing data or images, since a processor unit is assigned a unique number interval for each output channel. each The processor unit can thus create a simple routing table.
- the table for the processor unit numbered 123 is as shown in the routing table 4600 in FIG. 46.
- the locally generated information is communicated to the portal processor by means of MessCollectlnfo messages, which contain the following message parameters:
- Processor unit is specified by the portal processor
- Processor units are sent as soon as the respective processor unit has been numbered.
- the pixel processor can on the one hand map pixel images onto the real pixel field (sampling) and on the other hand route this image data with the help of the pixel numbers.
- the routing duration with which the routing trees are evaluated then also results directly from this routing table.
- the portal processor sends messages of the type MessRGB with the following parameters:
- the color information for this pixel for example red-green-blue values.
- Fig. 47 shows an example of an image representation on the pixel arrangement.
- the display is independent of the selected routing tree.
- routing matrices The selection and evaluation of routing matrices was described previously, that is to say essentially of routing routes.
- the evaluation criterion was the routing duration. Since a real combinatorial optimization cannot usually be carried out in a short time due to the complexity, an alternative was presented above.
- the freely selectable parameter is the weight g.
- this process can also be carried out several times by the portal processor with different weights g.
- routing that has the shortest routing duration can then finally be used.
- the portal processor uses the message MessRetry, which deletes all channels, color regions and color distances, as in Fig. 48 is shown.
- the MessRetry message is provided with the parameter "stamp", the value of which is not identical to the corresponding stored parameter of the processor unit. In other words, the portal processor uses a different parameter "stamp" each time it is reset.
- the own stamp parameter is set to the value of the stamp parameter value "stamp" contained in the MessRetry message.
- Additional MessRetry messages 4802 are transmitted over all connections, with the exception of the connection to the processor unit sending the MessRetry message, as shown in FIG.
- an error can only consist in the fact that a previously connected neighboring processor is no longer is achievable. However, it cannot judge whether only the connection to this neighboring processor or whether the neighboring processor itself has failed. In the event of such an occurrence, however, an error message, hereinafter referred to as the MessError message, can be sent to the portal processor, which identifies it itself, preferably using its own pixel number as the message parameter and which additionally contains the number of the newly failed connection.
- a possible reaction of the portal processor to such a message is a global reset of the pixel arrangement with the help of a measurement reset message.
- each pixel processor forwards this message to all neighboring processors and deletes all data that have been determined in the organization. To terminate this process, each pixel processor should adhere to a certain dead time, before which it does not react to further messages. The dead time prevents the distribution of the MessReset message from being repeated an infinite number of times.
- Fig. 51 gives an overview of the messages used and their respective parameters.
- FIG. 49 shows an additional exemplary embodiment of the invention, in which the processor units 4901 are arranged in a matrix in a first hierarchical level and are fully meshed with one another.
- the processors 4901 of the pixel arrangement 4900 in this case have a square, preferably a square shape and are controlling and reading coupled with a group of pixels, that is, pixels or sensor elements.
- each processor for controlling or reading out 4 * 4 pixels 4902, which are each grouped into a pixel block 4903, is coupled.
- the individual pixel group processors are networked with one another in an orthogonal network by local closest-neighbor connections 4904.
- One or more connections can run between two processors 4901, for example, to enable bidirectional data transmission or separate distribution of the supply voltages.
- the layer of pixels 4902 contains the individual pixel elements, each pixel block 4903 being controlled by means of a conventional matrix control, as is shown, for example, in FIG. 50.
- the matrix controller 5000 in FIG. 50 shows an example of a pixel block 5001 and a column addressing unit, which is designed as a shift register 5002, and a row addressing unit 5003, which is also designed as a shift register.
- the data are fed via a data source 5004 to the input of the shift register 5001 of the column addressing unit and to a clock generation unit 5005, which is connected on the output side to the
- Input of the column addressing unit 5003 is coupled.
- Data transmission is carried out over only one line, the clock signals also being obtained from the data signal itself.
- the pixel group processors can be meshed orthogonally with one another, but other meshings are also possible, in particular a hexagonal meshing as explained above.
- the pixel group processors can also exchange your messages in any format. However, they preferably exchange message blocks with one another, which may contain address codes, for example, with the aid of which the image information contained in data packets can then be passed from processor to processor. Defects in the matrix can also be avoided in this way, which is not possible with rigid x / y addressing via row lines and column lines.
- Information distribution also take on other tasks, such as compression or decompression of
- the architecture can also be used for large-area sensor arrays, such as fingerprint sensors, touchpads or
- Font recognition sensors are used.
- each pixel group processor can wait for an event, i.e., input with a pen, etc., to occur in a pixel group and then this data send or route to the edge of the respective matrix. In this way it can be avoided that the entire sensor surface must always be scanned by an external addressing unit. This clearly corresponds to a local triggering by an event instead of a global image evaluation.
- the pixel group processors can, for example, be converted into a suitable one with the aid of a technique such as, for example, the fluidic soap assembly as described in [3]
- Carrier substrate are introduced, as described according to the first embodiment.
- connections between the processors and the sensor or display matrices can then be applied to the carrier substrate with the processors in further process steps.
- the upper functional layers can preferably be implemented by means of printable circuits such as are provided in polymer electronics.
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Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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DE10158784 | 2001-11-30 | ||
DE10158781 | 2001-11-30 | ||
DE2001158784 DE10158784B4 (de) | 2001-11-30 | 2001-11-30 | Verfahren zum Bestimmen eines Abstands von Prozessoreinheiten zu mindestens einer Referenzposition in einer Prozessor-Anordnung und Prozessor-Anordnung |
DE2001158781 DE10158781A1 (de) | 2001-11-30 | 2001-11-30 | Pixel-Anordnung |
PCT/DE2002/004373 WO2003048953A2 (de) | 2001-11-30 | 2002-11-28 | Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung |
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EP1449110A2 true EP1449110A2 (de) | 2004-08-25 |
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EP02798255A Withdrawn EP1449110A2 (de) | 2001-11-30 | 2002-11-28 | Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung |
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US (1) | US20050078115A1 (de) |
EP (1) | EP1449110A2 (de) |
WO (1) | WO2003048953A2 (de) |
Families Citing this family (14)
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US7185225B2 (en) * | 2002-12-02 | 2007-02-27 | Marvell World Trade Ltd. | Self-reparable semiconductor and method thereof |
US7340644B2 (en) * | 2002-12-02 | 2008-03-04 | Marvell World Trade Ltd. | Self-reparable semiconductor and method thereof |
US20060001669A1 (en) * | 2002-12-02 | 2006-01-05 | Sehat Sutardja | Self-reparable semiconductor and method thereof |
DE10335819A1 (de) * | 2003-08-05 | 2005-03-17 | Infineon Technologies Ag | Prozessor-Anordnung, Textilgewebestruktur, Flächenverkleidungsstruktur und Verfahren zum Übertragen von elektronischen Nachrichten zwischen Prozessoren einer Prozessor-Anordnung |
AU2006201825B2 (en) * | 2005-05-02 | 2012-01-19 | Roads And Maritime Services | Variable Message Sign |
DE102005052005B4 (de) * | 2005-10-31 | 2007-10-18 | Infineon Technologies Ag | Prozessor-Anordnung |
US20080043003A1 (en) * | 2006-08-17 | 2008-02-21 | Vogsland Robin O | Smart display pixel |
US8718079B1 (en) | 2010-06-07 | 2014-05-06 | Marvell International Ltd. | Physical layer devices for network switches |
US9153171B2 (en) * | 2012-12-17 | 2015-10-06 | LuxVue Technology Corporation | Smart pixel lighting and display microcontroller |
DE102017106812B4 (de) | 2016-05-09 | 2018-01-11 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler LED-Sensor-Bänder |
DE102017106811B4 (de) | 2016-05-09 | 2018-01-11 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler LED-Bänder |
DE102017106813B4 (de) | 2016-05-09 | 2018-01-18 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler Sensor-Bänder |
DE102017109247B4 (de) | 2017-04-28 | 2024-05-08 | Elmos Semiconductor Se | Verfahren zur Bestimmung der physikalischen Position einer Leuchtmittelgruppe innerhalb eines eindimensionalen Leuchtbands mit mehreren Leuchtmittelgruppen |
DE102018102998A1 (de) * | 2018-02-09 | 2019-08-14 | Infineon Technologies Ag | Vorrichtung, Verfahren und Computerprogramm zum Vergleichen der Ausgabe von Sensorzellen |
Family Cites Families (9)
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JPS63240667A (ja) * | 1987-03-28 | 1988-10-06 | Nippon Telegr & Teleph Corp <Ntt> | 並列デ−タ処理装置 |
US5262771A (en) * | 1988-03-03 | 1993-11-16 | U.S. Philips Corporation | Method for addressing processor units |
US5600354A (en) * | 1992-04-02 | 1997-02-04 | Hewlett-Packard Company | Wrap-around flex with address and data bus |
US5917464A (en) * | 1994-10-18 | 1999-06-29 | Xerox Corporation | Combination of 2-D detector array with display for image processing |
US5644327A (en) * | 1995-06-07 | 1997-07-01 | David Sarnoff Research Center, Inc. | Tessellated electroluminescent display having a multilayer ceramic substrate |
DE19710855A1 (de) * | 1997-03-15 | 1998-10-01 | Dambach Werke Gmbh | Leuchtdiodenmatrix-Anzeigevorrichtung |
US5941714A (en) * | 1997-09-23 | 1999-08-24 | Massachusetts Institute Of Technology | Digital communication, programmable functioning and data transfer using modular, hinged processor elements |
US6240478B1 (en) * | 1998-10-30 | 2001-05-29 | Eaton Corporation | Apparatus and method for addressing electronic modules |
US6728862B1 (en) * | 2000-05-22 | 2004-04-27 | Gazelle Technology Corporation | Processor array and parallel data processing methods |
-
2002
- 2002-11-28 EP EP02798255A patent/EP1449110A2/de not_active Withdrawn
- 2002-11-28 WO PCT/DE2002/004373 patent/WO2003048953A2/de not_active Application Discontinuation
- 2002-11-28 US US10/496,696 patent/US20050078115A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
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See references of WO03048953A3 * |
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WO2003048953A3 (de) | 2003-11-06 |
US20050078115A1 (en) | 2005-04-14 |
WO2003048953A2 (de) | 2003-06-12 |
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