Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
  • G05F1/10—Regulating voltage or current
  • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

• the present invention relates to a voltage regulation circuit intended to regulate a voltage disturbed by a phenomenon known as "latch-up".
• FIG. 1A A circuit of this type is described in the document GB 2 298 939, and is represented in FIG. 1A of the present description.
• This circuit includes a control transistor Ql connected in series between an input terminal I and an output terminal 0, and an output voltage detector D consisting of two resistors Ra and Rb connected in series between the output terminal 0 and the mass of the circuit.
• a voltage corresponding to the output voltage detected by the detector D is compared to a reference voltage E3 by an operational amplifier AO, and the output voltage of the latter is applied to the base terminal of a transistor Q2.
• a base current of the control transistor Ql can be controlled by the output voltage of the operational amplifier AO, via the transistor Q2, so that the impedance of the control transistor Ql is controlled to provide a predetermined voltage at output terminal O.
• a problem encountered during the operation of such a circuit lies in the involuntary appearance of so-called "latch-up" phenomena which occur in an electronic component of the circuit, following external disturbances such as the supply of an electrical voltage, an electric current or radiation.
• latch-up is commonly used to refer to any phenomenon occurring in an integrated circuit following external disturbances such as the supply of a voltage, current or radiation.
• devices for detecting the "latch-up" phenomenon in a substrate and, in particular, devices analyzing a current liable to be disturbed by said phenomenon.
• a device of this type is described in the Japanese patent application published under No. 5,326,825 in the name of FUNAI ELECTRIC CO LTD, and is represented in FIG. 1B of the present description.
• This device comprises an integrated circuit ICI at a first terminal of which a supply voltage Vdd is supplied, by means of a bipolar transistor T1, and to the second terminal of which is connected a resonant circuit consisting of a resistor R3 and of a capacitor C3.
• An integrated detection circuit IC2 comprises a ground terminal, a first terminal on which the supply voltage Vdd is supplied, and a second terminal connected to said resonant circuit as well as to the base terminal of a bipolar transistor T2 by a resistance R2.
• the base terminal of the transistor T1 is connected to the collector terminal of the transistor T2 by a resistor Ri, and the emitter terminal of the transistor T2 is grounded.
• An advantage of the circuit according to the present invention is to provide a voltage regulation circuit having a slightly complex structure, which makes it cheap.
• Another advantage of the circuit according to the present invention is to provide a circuit comprising voltage comparison means at the input of which the regulated voltage is supplied, these means being arranged so as to define two voltage thresholds capable of being predetermined for meet user requirements.
• FIGS. 1A and 1B already cited represent two voltage regulation circuits according to the prior art; - Figure 2 shows a preferred embodiment of a voltage regulation circuit according to the present invention; Figure 3 shows in detail the preferred embodiment of the detection means of the circuit of Figure 2; FIG. 4 represents the relationship between three voltages present in the voltage regulation circuit according to the preferred embodiment of the present invention; and - Figures 5A and 5B show the timing diagrams of the regulated voltage and the signal supplied by the voltage regulation circuit according to the preferred embodiment of the present invention.
• FIG. 2 represents a preferred embodiment of a circuit 1 according to the present invention.
• Circuit 1 comprises an input terminal I and an output terminal 0 from which a regulated voltage Vreg must be supplied, the voltage Vreg being supplied so as to be substantially equal to a voltage level Vo.
• the circuit 1 also comprises a bipolar transistor 2, two capacitors 3 and 9, a resistor 5, a Zener diode 6, and voltage detection means 11.
• the bipolar transistor 2 typically comprises a collector terminal C, a terminal d emitter E and a base terminal B, terminals C and E being connected respectively to terminals I and 0.
• Resistor 5 is connected between terminal B and terminal C of transistor 2.
• the Zener diode 6 is arranged so that 'it provides a voltage having a value chosen so as to form the voltage level Vo on the output terminal 0.
• Capacitors 3 and 9 are connected between input terminal I and ground, and between output terminal 0 and ground, respectively. Those skilled in the art will note that the capacitor 3 is conventionally used as a deworming capacitor, and that the capacitor 9 is conventionally used as a smoothing and / or deworming capacitor. The capacitor 3 is only used as an improvement in the present invention, and therefore does not have any limiting nature for the present invention.
• the means 11 comprise an input terminal connected to terminal 0, so as to receive the input voltage Vreg, a ground terminal, and an output terminal connected to terminal B, so as to output a voltage of Vres control to control the transistor 2.
• the means 11 are arranged so that they detect if the voltage Vreg is disturbed by a "latch-up" phenomenon and, if necessary, command an initialization of this voltage at its voltage level initial Vo, as explained in more detail below. Indeed, following numerous experiments, the applicant of the present invention has found that one of the most effective solutions for eliminating a "latch-up" phenomenon in an integrated circuit consists in bringing the level of the voltage to the ground potential. power supply to the integrated circuit disturbed by said phenomenon, for a sufficient time for this circuit to drop below a certain voltage threshold.
• the voltage regulation circuit comprises voltage detection means which, following a "latch-up" type disturbance, bring the regulated voltage to ground potential, which has the effect of remove this disturbance.
• FIG. 3 shows in detail the preferred embodiment of the means 11, according to the present invention.
• the means 11 comprise reference voltage supply means 20 for supplying a reference voltage Vref from the voltage Vreg, a voltage divider 21 intended to supply two corrected regulated voltages Vreg 'and Vreg "from the regulated voltage Vreg, two voltage comparators 23 and 22 for comparing the voltage Vref with the voltages Vreg 'and Vreg ", respectively, and control means 24 for supplying, if necessary, the voltage Vres capable of controlling the transistor 2, and of regulating the voltage Vreg.
• the means 20 comprise an input terminal connected to the input terminal of the means 11 (that is to say to the terminal 0), so that the means 20 receive the input voltage Vreg, a ground terminal connected to ground, and an output terminal connected to comparators 22 and 23, so that the means 20 provide the output voltage Vref.
• the means 20 are known in the art, see for example the articles "CMOS Analog Integrated Circuits Based on Weak Inversion Operation", by E. Vittoz et al, IEEE Journal of Solid States Circuits, vol. SC-12, No. 3, June 1977, and "CMOS Voltage References Using Latéral Bipolar Transistors ", by M. Degrauwe et al, IEEE Journal of Solid States Circuits, vol. SC-20, No 6, December 1985.
• FIG. 4 represents a curve 31 corresponding to the relationship between the voltage Vref and the voltage Vreg.
• the means 20 are arranged so that, for a value of the input voltage Vreg greater than 1.5 V, the output voltage Vref is substantially equal to a voltage threshold Vr 'of the order of 1.2 V, and that there is a voltage plateau on which the voltage Vref is substantially equal to a voltage threshold Vr ", for low values of the voltage Vreg.
• a first voltage level A'Vr ' is defined as the voltage level below which a latch-up phenomenon is supposed to occur.
• a second voltage level A "Vr” is also defined as the voltage level below which a "latch-up” phenomenon is suppressed.
• the voltage levels A'Vr 'and A “Vr” are predetermined values according to specificities specific to the requirements of the user.
• the voltage divider 21 is formed by a resistive bridge consisting of three resistors 25, 26 and 27 connected in series between the output terminal 0 and the ground.
• the connection point between the two resistors 26 and 27 is connected to a first input of the comparator 23, so as to supply the input voltage Vreg '.
• This voltage is, by definition, proportional to the voltage Vreg, the proportionality ratio, referenced by A ', being predetermined and dependent on the values of the resistors 27, 26 and 25.
• FIG. 4 represents a curve 32 corresponding to the relationship between the voltage Vreg 'and the voltage Vreg.
• connection point between the two resistors 25 and 26 is connected to a first input of the comparator 22, so as to supply the input voltage Vreg ".
• This voltage is, by definition, proportional to the voltage Vreg, the proportionality ratio, referenced by A ", being predetermined and dependent on the values of resistors 25, 26 and 27.
• FIG. 4 represents a curve 33 corresponding to the relationship between the voltage Vreg" and the voltage Vreg.
• Each comparator 23, 22 comprises a first input terminal on which is supplied a corrected regulated voltage Vreg ', Vreg ", respectively, as described above, and a second input terminal on which is supplied the voltage Vref , as also described above.
• the comparator 23 compares the voltage Vreg 'with the voltage Vref, while the comparator 22 compares the voltage Vreg "with the voltage Vref.
• Each comparator 22, 23 further comprises an output terminal connected to a respective input terminal of the control means 24.
• the control means 24 further comprise an output terminal serving as an output terminal of the means 11, so as to switch the voltage Vres, when one of the comparators 22, 23 switches, which controls the regulation of the voltage Vreg, as will be described in more detail.
• the means 24 can be formed by a flip-flop known per se to those skilled in the art, and arranged so that it switches to output a logic voltage level low enough to bring the transistor 2 into a blocked state, or a logic voltage level high enough to bring transistor 2 into a conductive state, these two logic levels being designated “0L” and "IL", respectively.
• the operation of circuit 1 according to the present invention will be explained with reference to Figures 5A and 5B.
• FIGS. 5A and 5B schematically represent timing diagrams of the voltages Vreg and Vres present in the circuit 1, respectively.
• the voltage Vreg is substantially equal to the voltage level Vo, and the voltage detection means 11 output a logic level "IL” as voltage Vres. Consequently, the transistor 2 is kept in a conductive state, so that the voltage between its base and emitter terminals subtracted from the voltage across the terminals of the Zener diode 6 is equal to the voltage level Vo.
• a "latch-up" phenomenon is therefore declared responsible for the loss of control over the Vreg voltage.
• the voltage Vreg' (curve 32) becomes lower than the voltage threshold Vr '(curve 31), which causes the switching of the comparator 23.
• the means 24 advantageously bring the voltage Vres to "0L", this logic level being sufficient to block the transistor 2.
• the integrated circuit under the influence of the "latch-up” phenomenon is not therefore more supplied under the voltage level Vo. This has the effect of significantly lowering the voltage Vreg and, consequently, the voltage Vref.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Continuous-Control Power Sources That Use Transistors (AREA)
• Details Of Television Scanning (AREA)
• Electronic Switches (AREA)
• Power Conversion In General (AREA)
• Control Of Electrical Variables (AREA)
• Measurement Of Current Or Voltage (AREA)
• Control Of Voltage And Current In General (AREA)

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• 1997
  • 1997-05-12 EP EP97107722A patent/EP0878752A1/de not_active Withdrawn
• 1998
  • 1998-05-11 KR KR1019997010379A patent/KR20010012426A/ko not_active Application Discontinuation
  • 1998-05-11 AT AT98929294T patent/ATE217102T1/de not_active IP Right Cessation
  • 1998-05-11 US US09/423,228 patent/US6184664B1/en not_active Expired - Fee Related
  • 1998-05-11 JP JP54879098A patent/JP2001525091A/ja active Pending
  • 1998-05-11 WO PCT/EP1998/002749 patent/WO1998052111A1/fr not_active Application Discontinuation
  • 1998-05-11 CA CA002289935A patent/CA2289935A1/en not_active Abandoned
  • 1998-05-11 EP EP98929294A patent/EP1010048B1/de not_active Expired - Lifetime
  • 1998-05-11 DE DE69805188T patent/DE69805188T2/de not_active Expired - Fee Related

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