EP0951692A1 - Element support pour une puce de semi-conducteur a inserer dans une carte a puce - Google Patents

Element support pour une puce de semi-conducteur a inserer dans une carte a puce

Info

Publication number
EP0951692A1
EP0951692A1 EP98956777A EP98956777A EP0951692A1 EP 0951692 A1 EP0951692 A1 EP 0951692A1 EP 98956777 A EP98956777 A EP 98956777A EP 98956777 A EP98956777 A EP 98956777A EP 0951692 A1 EP0951692 A1 EP 0951692A1
Authority
EP
European Patent Office
Prior art keywords
connections
carrier element
element according
semiconductor chip
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98956777A
Other languages
German (de)
English (en)
Inventor
Frank PÜSCHNER
Jürgen Fischer
Josef Heitzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0951692A1 publication Critical patent/EP0951692A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

  • the invention relates to a carrier element for a semiconductor chip with at least two connections, in particular for installation in chip cards, the element having a wrapping compound that surrounds and protects the semiconductor chip, the connections are made of conductive material and have a reduced thickness at the mutually facing ends , the cross section having only one step.
  • the semiconductor chip is arranged in the region of this section of reduced thickness on the connections and is mechanically connected to them.
  • Such a support element is known from JP 08-116016 A from Patent Abstracts of Japan.
  • this known carrier element is not suitable for installing m chip cards, since it is provided on both sides with encapsulation compound and the connections are not accessible in a suitable manner.
  • No. 5,134,773 discloses a carrier element with contact surfaces made of conductive material in the form of a so-called leed frame, in which the semiconductor chip is glued to a centrally arranged chip island and is electrically connected to peripherally arranged contact surfaces by means of bonding wires.
  • the semiconductor chip is surrounded by a sheathing compound protecting it and the bond wires, which also holds the contact areas in position. Since the contact surfaces must be freely accessible from the side facing away from the chip, the wrapping aces are only present on one side.
  • the contact surfaces on the side facing away from the chip have undercuts in the area of the slots which are electrically insulating from one another. fertilize, which are filled in by the encapsulation and create a kind of riveted connection.
  • the carrier element described in US Pat. No. 5,134,773 is designed for so-called contact-type chip cards, that is to say it has contact surfaces lying on a surface of the chip card and accessible from outside for a reading device, but it is readily possible and also known to provide only two connections. which can be electrically connected to a coil arranged on the card or on a card layer.
  • connections in Zan. and design to provide such that they are equally suitable for both a connection to a coil or antenna and a reader.
  • a typical structure for a chip card for contactless use is composed as follows:
  • the coil support film has a thickness of approximately 200 ⁇ m
  • the two core films each have a thickness of approximately 100 ⁇ m
  • two printing films on each side have a thickness of approximately 150 ⁇ m
  • two scratch-proof films a thickness of about 50 ⁇ m each. Together, this results in a thickness of approximately 800 ⁇ m in accordance with ISO standard 7816. This results in a necessary support element phone of less than 400 ⁇ m as well as a possible expansion in the card level.
  • the object of the invention is to provide a support element that has a low height and an improved bruising behavior and is easy to produce.
  • connections which are part of a holder frame, a so-called lead frame, during the assembly of the semiconductor chip and the encapsulation of the chip and the connecting lines, have a section of reduced thickness such that the cross section has only one step on one side.
  • the section of reduced thickness is produced in accordance with the invention by embossing. A reduction in the thickness to 50 is necessary. In most cases, the nominal connection is sufficient.
  • a main surface of the connections is flat, while the opposite surface has a step.
  • the semiconductor chip is arranged in the region of this section. It can be arranged on the side of the step or on the opposite side.
  • the chip is expediently mounted with its active side oriented away from the connections if it is arranged on the step side of the connections. If it is located on the side opposite the step side, it is from
  • Chipmsel has not only the advantage ge ⁇ ringerer thickness of the carrier element but also a ⁇ en BES sere anchoring of Umhullungsmasse ⁇ en with terminals, since the Umhullungsmasse can enclose the Cnip from both sides and a good connection from the chip to the terminals is .
  • the chip capsule By eliminating the chip capsule, there are no longer any notch effects, so that better breaking strength properties result.
  • connection surfaces Due to the desired low height of the support element, one of the connection surfaces will be exposed and will be available for contacting.
  • a chip card especially a laminated one
  • connections can protrude beyond the dimensions of the enveloping mass and form contact tabs for antenna connections there.
  • This is advantageous for an assembly in which the antenna coil is applied to a carrier film.
  • the carrier film advantageously has a recess or recess in which the enveloping mass comes to lie, while the connections or, in this case, the contact tabs come to rest on the coil carrier film on the coil connections.
  • connection only in the area of the enveloping mass, which has the advantage that a carrier element of this type can also be retrofitted into an already laminated card which, however, has a cutout.
  • the ends of the antenna coil are expediently located in this recess in order to be able to be connected in a simple manner to the support element connections, for example by gluing or soldering or also by resilient connecting parts.
  • a support element that only has such contact surfaces instead of contact tabs projecting beyond the edge can also be applied directly to a coil support film.
  • the corresponding core film of the card laminate should have a recess.
  • the contact tabs can advantageously have a widened end in order to be able to be better connected to connections of wound coils.
  • connection lugs are bent again at right angles, preferably in the other direction, an even better anchoring results. This also creates additional contact surfaces that can be used for an alternative installation.
  • FIG. 1-6 different cross-sectional embodiments of a support element according to the invention
  • Figure 7 em carrier element with contact tabs for mounting on a coil carrier film
  • Figure 8 em carrier element with contact surfaces for mounting on a coil carrier film or directly in a chip card.
  • FIG. 1 shows a support element according to the invention in cross-section, as indicated in FIG. 7.
  • Two connections 1 are arranged along opposite edges of the carrier element. They serve on the one hand as an Au surface for a semiconductor chip 2 and on the other hand for contacting it from outside of the carrier element. For this purpose, they are connected to the semiconductor chip 2 via bonding wires 4.
  • the semiconductor 2 is mechanically connected to the connections 1 with an adhesive 3.
  • the semiconductor chip 2 and the bonding wires 4 are encapsulated or encapsulated with a coating compound 5.
  • the wrapping mass 5 advantageously has a light color which does not show through the layers of a chip card, as is the case with black masses which are usually available on the market.
  • connections 1 are advantageously arranged in the area of diagonal corners of the carrier element in order to serve a uniform and balanced base for the semiconductor chip 2 during the installation.
  • the connections 1 are included for the purpose of the installation a frame holding it, a so-called leadframe, is connected and is punched out of the chip after assembly and overmolding or casting.
  • only two connections 1 are provided, since these carrier elements are particularly suitable for contactless chip cards.
  • Umhullungsmasse 5 can envelop the ge ⁇ entire chip 2 and thus a better adhesion of the at ⁇ connections 1 cause the carrier element, since they are retained to a large extent by the adhesive joint 3, not only because of the adhesion forces between the encapsulation compound 5 and the connections 1.
  • connections 1 An even better anchoring of the connections 1 is achieved if they are angled, as shown in FIG. 2.
  • a first section 1c of the connections 1 is bent at an approximately right angle to the chip 2 hm.
  • a second gate l ⁇ can also be bent in the right direction m in the other direction. This creates a further contact surface that is accessible from the outside, so that such a support element is also suitable for so-called combination cards, since it can be connected to a coil from one side and can be contacted from the other side by a reading device.
  • more than two connections are required for this. It was enough, however, to turn only two.
  • the main aspect of the carrier element according to the invention can be seen in a section 1 a of the connections 1, which has a smaller thickness compared to the nominal thickness, but a step in cross section is only on one side of the connections 1.
  • the overall height of the carrier element can be reduced by approximately half the connection thickness if the semiconductor chip 2 is placed in the region of these sections with a smaller thickness 1 a. Since these sections 1 a can be kept small, the mechanical properties of the connections 1 are not impaired.
  • the semiconductor chip 2 is arranged on the side of the cross-sectional step of the connections 1, the active side of the semiconductor chip 2, that is to say the side that the Integrated circuits, oriented away from the connections 1.
  • FIGS. 3 and 4 show variants in which the semiconductor chip 2 is arranged on the side of the connections 1 opposite the cross-sectional step , the active side being oriented toward the connections 1 hm.
  • the bonding wires 4 are led erfmdungsgeseller manner to the sections of lesser thickness la, so that it must be provided by the loop height of the bonding wires, no additional height of the Tra ⁇ gerelements.
  • a further saving in height can be achieved if the chip back side is not provided with encapsulation compound 5, as shown in FIG. 4. This is possible because the active side of the semiconductor chip 2 is oriented towards the connections 1 nm.
  • FIGS. 5 and 6 show further assembly variants in which the semiconductor chip 2 m is connected to the connections 1 using the so-called flip-chip technology.
  • the connection pads of the chip 2 are connected directly to the connection sections with a smaller thickness la.
  • the lowest height has the carrier element according to FIG. 6, in which the semiconductor chip 2 m flip-chip technology is mounted in the region of the gates of reduced thickness 1 a and the back of the chip remains uncovered by encapsulation compound 5.
  • FIG. 7 shows a possible installation variant of a carrier element according to the invention, a carrier film 7 for an antenna coil 8.
  • the carrier element has connections 1 with contact tabs, that is to say connections 1, which protrude beyond the edge of the encapsulation compound 5.
  • the contact lugs have widened ends 1b in order to enable better contacting with the coil connections 10.
  • the encapsulation mass 5 m, a recess 9 of the carrier film 7 is inserted, the contact lugs 1 coming into contact with the coil connections 10 m.
  • This mounting variant enables a particularly planar installation of a support element in a laminated card.
  • FIG. 8 shows a variant in which the connections 1 are designed as contact surfaces (which cannot be seen in the figure since they lie on the underside of the carrier element).
  • the sections protruding beyond the edge of the encapsulation compound 5 have been removed, for example already during the punching out of the lead frame.
  • the support element is placed on the coil support film 7 and contacted with the coil connections 10.
  • the upper core film of the chip card lammate must have a cutout.
  • This embodiment of the carrier element can, however, also be retrofitted to an already laminated or cast card 11 which has a recess 12 for this purpose.
  • the coil connections 10 can be seen, which, due to this preferred position, allow simple contacting with the support element connections 1.
  • Chip card 11 enables a so-called combination card to be produced in a simple manner, which on the one hand has contact surfaces for contacting a reading device, which lie on a surface of the chip card 11 and on the other hand contains a coil 8.
  • a carrier element according to FIG. 2 is particularly suitable for this.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Credit Cards Or The Like (AREA)
  • Die Bonding (AREA)

Abstract

Elément support pour une puce de semi-conducteur (2) comprenant au moins deux connexions (1), destiné notamment à être inséré dans une carte à puce (11) présentant une matière d'enrobage (5) protégeant la puce de semi-conducteur (2). Les connexions (1) sont disposées sur l'une des surfaces principales de la matière d'enrobage (5), uniquement le long de deux bords opposés. Elles sont réalisées en un matériau conducteur et présentent, à leurs extrémités tournées l'une vers l'autre (1a), une épaisseur réduite, la section n'étant étagée que d'un seul côté. La puce de semi-conducteur (2) est disposée sur les connexions (1), dans la zone de cette section d'épaisseur (1a) réduite, et reliée mécaniquement à celles-ci.
EP98956777A 1997-10-15 1998-09-17 Element support pour une puce de semi-conducteur a inserer dans une carte a puce Withdrawn EP0951692A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19745648A DE19745648A1 (de) 1997-10-15 1997-10-15 Trägerelement für einen Halbleiterchip zum Einbau in Chipkarten
DE19745648 1997-10-15
PCT/DE1998/002768 WO1999019832A1 (fr) 1997-10-15 1998-09-17 Element support pour une puce de semi-conducteur a inserer dans une carte a puce

Publications (1)

Publication Number Publication Date
EP0951692A1 true EP0951692A1 (fr) 1999-10-27

Family

ID=7845667

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98956777A Withdrawn EP0951692A1 (fr) 1997-10-15 1998-09-17 Element support pour une puce de semi-conducteur a inserer dans une carte a puce

Country Status (10)

Country Link
US (1) US6719205B1 (fr)
EP (1) EP0951692A1 (fr)
JP (1) JP3839063B2 (fr)
KR (1) KR20000069487A (fr)
CN (1) CN1122942C (fr)
BR (1) BR9806706A (fr)
DE (1) DE19745648A1 (fr)
RU (1) RU2216042C2 (fr)
UA (1) UA46136C2 (fr)
WO (1) WO1999019832A1 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19918852C1 (de) * 1999-04-26 2000-09-28 Giesecke & Devrient Gmbh Chipkarte mit Flip-Chip und Verfahren zu ihrer Herstellung
DE19940564C2 (de) * 1999-08-26 2002-03-21 Infineon Technologies Ag Chipkartenmodul und diesen umfassende Chipkarte, sowie Verfahren zur Herstellung des Chipkartenmoduls
DE19955537B4 (de) * 1999-11-18 2006-04-13 Orga Kartensysteme Gmbh Verfahren zur Herstellung eines Trägerelementes für einen IC-Baustein
DE60137117D1 (de) * 2000-02-22 2009-02-05 Toray Eng Co Ltd Kontaktlose ic-karte und verfahren zu ihrer herstellung
SG106050A1 (en) * 2000-03-13 2004-09-30 Megic Corp Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby
US6606247B2 (en) 2001-05-31 2003-08-12 Alien Technology Corporation Multi-feature-size electronic structures
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
FR2857483B1 (fr) * 2003-07-11 2005-10-07 Oberthur Card Syst Sa Carte a puce anti-intrusion
FR2869706B1 (fr) * 2004-04-29 2006-07-28 Oberthur Card Syst Sa Entite electronique securisee, telle qu'un passeport.
WO2006003548A2 (fr) * 2004-06-30 2006-01-12 Koninklijke Philips Electronics N.V. Carte a puce pour insertion dans un support
ATE517398T1 (de) * 2004-07-29 2011-08-15 Nxp Bv Modulbasiseinheit mit spannungsentlastungsmitteln
KR101038493B1 (ko) * 2004-11-12 2011-06-01 삼성테크윈 주식회사 극초단파용 라디오 주파수 인식태그 제조방법
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
FR2888371B1 (fr) * 2005-07-06 2007-10-05 Oberthur Card Syst Sa Support de donnees pliable a puce sans contact tel qu'un passeport
ATE496347T1 (de) * 2006-09-26 2011-02-15 Feinics Amatech Teoranta Verfahren für den anschluss einer antenne an einen transponderchip und entsprechendes einlagensubstrat
US8608080B2 (en) 2006-09-26 2013-12-17 Feinics Amatech Teoranta Inlays for security documents
US7707706B2 (en) * 2007-06-29 2010-05-04 Ruhlamat Gmbh Method and arrangement for producing a smart card
DE102008016274A1 (de) 2008-03-28 2009-10-01 Smartrac Ip B.V. Chipträger für ein Transpondermodul sowie Transpondermodul
DE102010041917B4 (de) * 2010-10-04 2014-01-23 Smartrac Ip B.V. Schaltungsanordnung und Verfahren zu deren Herstellung
CN114823550B (zh) * 2022-06-27 2022-11-11 北京升宇科技有限公司 一种适于批量生产的芯片封装结构及封装方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3019207A1 (de) * 1980-05-20 1981-11-26 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Traegerelement fuer einen ic-chip
DE3123198C2 (de) * 1980-12-08 1993-10-07 Gao Ges Automation Org Trägerelemente für einen IC-Baustein
DE3248385A1 (de) * 1982-12-28 1984-06-28 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit integriertem schaltkreis
JPH02303056A (ja) * 1989-05-17 1990-12-17 Mitsubishi Electric Corp 半導体集積回路の製造方法
FR2659157B2 (fr) 1989-05-26 1994-09-30 Lemaire Gerard Procede de fabrication d'une carte dite carte a puce, et carte obtenue par ce procede.
JPH04148999A (ja) * 1990-10-12 1992-05-21 Dainippon Printing Co Ltd Ｉｃカード
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
KR930014916A (ko) * 1991-12-24 1993-07-23 김광호 반도체 패키지
DE19527359A1 (de) * 1995-07-26 1997-02-13 Giesecke & Devrient Gmbh Schaltungseinheit und Verfahren zur Herstellung einer Schaltungseinheit
DE19532755C1 (de) * 1995-09-05 1997-02-20 Siemens Ag Chipmodul, insbesondere für den Einbau in Chipkarten, und Verfahren zur Herstellung eines derartigen Chipmoduls
FR2741191B1 (fr) * 1995-11-14 1998-01-09 Sgs Thomson Microelectronics Procede de fabrication d'un micromodule, notamment pour cartes a puces
KR0179925B1 (ko) * 1996-06-14 1999-03-20 문정환 리드프레임 및 그를 이용한 버텀 리드 반도체 패키지
DE29621837U1 (de) * 1996-12-16 1997-02-27 Siemens AG, 80333 München Trägerelement für Halbleiterchips
US6049463A (en) * 1997-07-25 2000-04-11 Motorola, Inc. Microelectronic assembly including an antenna element embedded within a polymeric card, and method for forming same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9919832A1 *

Also Published As

Publication number Publication date
BR9806706A (pt) 2000-04-04
JP2001507842A (ja) 2001-06-12
WO1999019832A1 (fr) 1999-04-22
CN1122942C (zh) 2003-10-01
JP3839063B2 (ja) 2006-11-01
CN1247616A (zh) 2000-03-15
US6719205B1 (en) 2004-04-13
RU2216042C2 (ru) 2003-11-10
KR20000069487A (ko) 2000-11-25
UA46136C2 (uk) 2002-05-15
DE19745648A1 (de) 1998-11-26

Similar Documents

Publication Publication Date Title
EP0951692A1 (fr) Element support pour une puce de semi-conducteur a inserer dans une carte a puce
DE19747105B4 (de) Bauelement mit gestapelten Halbleiterchips
EP1271399B1 (fr) Porteur de données avec circuit intégré
DE19743767B4 (de) Verfahren zum Herstellen eines Halbleiterchip-Gehäuses mit einem Halbleiterchip für Oberflächenmontage sowie ein daraus hergestelltes Halbleiterchip-Gehäuse mit Halbleiterchip
DE102011053871B4 (de) Multichip-Halbleitergehäuse und deren Zusammenbau
DE68921179T2 (de) Elektronisches Modul mit einer integrierten Schaltung für ein kleines tragbares Objekt, z.B. eine Karte oder ein Schlüssel und Herstellungsverfahren für solche Module.
DE68927295T2 (de) Kunstharzversiegeltes halbleiterbauelement
EP0965103B1 (fr) Module de carte a puce et carte a puce comportant ce dernier
DE10142120A1 (de) Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
WO2000048249A1 (fr) Composant a semiconducteur comportant un porte-puce avec des ouvertures pour la metallisation
DE102008046095A1 (de) Vereinzelter Halbleiterbaustein
DE3428881A1 (de) Verfahren zum herstellen einer integrierten schaltungsvorrichtung
DE69213269T2 (de) Metall-Basisplatte wie Wärmesenke für eine Plastikumhüllte Halbleiteranordnung mit erhöhten Teilen zum Löten von Erdschluss-Verbindungsdrähten
DE4040770A1 (de) Datentraeger mit integriertem schaltkreis
DE19543427C2 (de) Chipmodul, insbesondere zum Einbau in eine Chipkarte
EP0852807B1 (fr) Procede de connexion electrique d'une puce a semi-conducteur avec au moins une surface de contact
DE19752195A1 (de) Halbleiterelement mit einer Tragevorrichtung und einem Zuleitungsrahmen und einem damit verbundenen Halbleiterchip
DE19716342C2 (de) Verfahren zur Herstellung einer Chipkarte
DE602004004647T2 (de) Verfahren zum zusammenbauen eines elektronischen komponent auf einem substrat
DE69210423T2 (de) Halbleiteranordnung mit Plastikpackung
EP1278243A2 (fr) Module multi-puces sous forme d'assemblage de type COB, notamment une carte flash compacte avec grand capacité de mémoire et méthode de fabrication associée
EP1309998B1 (fr) Procede de connexion electrique d'un composant semi-conducteur et d'un assemblage electrique
DE19702186C2 (de) Verfahren zur Gehäusung von integrierten Schaltkreisen
DE102019127007A1 (de) Stapel elektrischer bauelemente und verfahren zur herstellung desselben
DE102021122591A1 (de) Mehrlagiges verbindungsband

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19990610

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT CH DE ES FR GB IT LI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

17Q First examination report despatched

Effective date: 20041029

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20080401