Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/4985—Flexible insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01039—Yttrium [Y]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01057—Lanthanum [La]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01078—Platinum [Pt]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01082—Lead [Pb]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• This invention relates generally to a tape automated lea bonding process for lead attachment to integrated circui devices and more particularly to a lead package and a reus able transport and test tape for receiving and transportin said lead package during fabrication of packaged integrate circuits.
• the format for the thin metal film or thin film layere tape includes an elongated tape with sprocket holes fo indexing the tape as the semiconductor chip is bonded t the thin leads and then advanced to various processin stations for encapsulation, testing and the like.
• Th tapes have widths ranging from 8 to 70 millimeters and ar provided on reels or strips.
• the tape portions which d not form leads for the integrated circuit package ar discarded when the integrated circuit package is severe from the tape. Generally, the discarded materials repre sent a significant cost of packaging.
• This invention provides a tape automated bonding process i which the lead package (lead pack) is a separate componen secured to a reusable transport tape.
• t is a further object of the present invention to provid a reusable tape for receiving a lead pack, presenting th lead pack to an integrated circuit for bonding the leads o the lead pack to the integrated circuit and then presentin the lead pack and integrated circuit to succeeding station for testing and encapsulation.
• a reusable transport and test tape which in cludes a plurality of leads adapted to receive and connec to the leads of the lead pack and to position the lead pac for reception of an integrated circuit for bonding of lea pack leads to the contact pads of the integrated circui and to move the lead pack and integrated circuit int succeeding processing stations where the circuit is pac aged and tested, and then excised.
• a lead pack which includes rectangular frame of insulating material and a plurality leads imbedded in said frame and extending inwardly a outwardly therefrom for attachment to an associated int grated circuit and for attachment of the leaded integrat circuit to an associated printed wiring board or like ci cuit.
• the insulating frame serves as a dam or seali means in an encapsulating process.
• An additional fra stabilizes and positions the outwardly extending ends the leads.
• Figures 1A and IB show a flow chart illustrating t formation of a lead pack and transport of the lead pack the transport and test tape and insertion and testing of integrated circuit and protective encapsulation thereof.
• Figure 2A shows an insulating tape which has been pe forated to define a lower lead frame.
• Figure 2B shows a lower lead. frame excised from t tape of Figure 2A.
• Figure 3A shows an insulating tape which has be perforated to define an upper lead frame and upper le support.
• Figure 3B shows the upper lead frame and upper le support excised from the tape of Figure 3A.
• Figure 4 shows a portion of a thin metal film such a copper perforated to define leads.
• Figure 5 is a sectional view taken along the line 5 of Figure 4.
• Figure 6 is a sectional view taken along the line 6 in Figure 4, showing the forming of a lead bump or dimp that will become the inner end of the lead pack lead.
• Figure 7 is a sectional view of a lead with protective plating.
• Figure 8 is a view showing a portion of the perforated metal film with a lower insulating frame attached.
• Figure 9 is a sectional view taken along the line 9-9 of Figure 8.
• Figure 10 is a view showing a portion of perforated metal film with both the lower and the upper insulating frame attached.
• Figure 11 is a sectional view taken along line 11-11 of Figure 10.
• FIGS. 12A-12F show the steps in imbedding the leads in the lower insulating frame.
• Figure 13 shows the perforated metal film with the center portion excised to provide cantilevered and plated lead portions.
• Figure 14 is a sectional view taken along the line 14- 14 of Figure 13.
• Figure 15 is a sectional view showing the lead of Fig. 14 with a conductive adhesive applied.
• Figure 16 is a sectional view showing outer leads ex ⁇ cised from the perforated metal film to thereby form a lead pack.
• Figure 17 is an enlarged view of a portion of the tape transport illustrating the conductive pattern between the center window and the outer test pads.
• Figure 18 shows the lead pack with the leads secured to the tape transport conductors with a conductive adhesive.
• Figure 19 is a sectional view taken along the line 19- 19 of Figure 18 showing the connection of the lead pack leads to the transport tape leads.
• Figure 20 is a partial view showing the cantilevered lead pack inner leads attached to a semiconductor chip.
• Figure 21 is a sectional view taken along the line 21- 21 of Figure 20 showing the connection of a bumped o dimpled inner lead to a chip contact pad. -5-
• Figure 22 shows a lower package body attached to th lead pack frame.
• Figure 23 is a sectional view taken along the line 23 23 of Figure 22 showing the lower housing.
• Figure 24 is a view showing the application of th upper housing body to the lead pack frame.
• Figure 25 is a sectional view taken along the line 25 25 of Figure 24 showing the upper housing portion.
• Figure 26 shows the leads severed from the transpor tape.
• Figure 27 shows bending of the outwardly extendin lead portions to form feet for attachment to an associate circuit.
• Figure 28 is an enlarged view of a portion of packaged semiconductor device attached to a printed wirin board.
• th lead package includes a frame of insulating material whic supports conductors in spaced relationship with one en cantilevered inside the frame and one end extending out wardly.
• the transport tape includes leads, to be described present ly, which splay outwardly from the window to test pads.
• the process of the present invention comprises forming th lead pack 11 with its bumped, plated and spaced leads an placing the lead pack 11 within the window 13 with th outwardly extending ends of the leads connecting to th transport tape leads.
• the transport tape 12 include sprocket holes 14 which are used to index the tape as i moves in the direction of the arrow 16 to first present th windows for reception of a lead pack 11 then to advance t a station where a semiconductor chip is bonded to th inwardly extending ends of the lead pack leads then to testing station.
• the lead pack and chip move to stations where upper and lower housing portions are applied.
• Each of the operations can be followed by a testing step using the tape test pads to assure that the packaging operation has not altered the electrical properties or relationship between the lead pack and integrated circuit chip.
• the packaged chip then moves to a burn in station, if such is required, and then to an excise station where the leads are severed from the transport tape and the leads bent to form attachment feet for the packaged semiconductor integrated circuit.
• the packaged circuit can then be mounted on a printed circuit board or in other electrical circuits.
• the lead pack lead support frame includes upper and lower frame portions adhered to one another to embed the leads.
• the lower frame portion is formed from an insulating material 16 which includes sprocket openings 17 and is moved sequentially through processing stations.
• the tape may be a polyimide, acry ⁇ lic, polycarbonate, polyester, epoxy or other thermally responsive insulating and adhesive material.
• a frame 18 is formed by first forming windows 19 in the tape.
• Figure 2A and thereafter excising the central portion 21 to form the frame 18.
• the upper frame portion 22 is formed from a similar insulating material 23 of the same type as the tape 16.
• the tape 23 includes sprocket openings 24 for index ⁇ ing.
• the tape is perforated to form windows 26 and 27 and then the central portion 28 is excised to leave a frame having an inner frame portion 29 to mate with the lower frame portion 18 and an outer por ⁇ tion 30 which is adapted to engage and support the ends of the leads as will be presently described.
• the thin metal leads for the lead pack are formed from a thin metal tape (Figure 1A) , such as a copper tape, 3 which includes sprocket holes 32 for indexing the tape a it passes various stations.
• a thin metal tape Figure 1A
• the tape is first punched. -7- perforated or etched to form a plurality of windows 33 a indexing holes 35 diagonally across from one another wi one hole being round, as shown, and the other (not show being a rectangular slot.
• the windows 33 define thereb tween elongated leads 34 which have a narrow end 36.
• T enlarged sectional view of Figure 5 shows the beam lead This first step is schematically illustrated at 38, Figu 1A.
• the tape is then advanced and indexed to a seco station 39 where the perforated foil is presented to forming die which forms bumps, or dimples, in the narr end 36 of the leads.
• the die co prises a lower die portion 41 which receives the leads a a forming punch 42 which deforms the leads into the low die to form dimples which are spaced from the sides of t lead.
• the perforated punched tape is then moved to station 43 where the leads are plated with gold, tin other material 44 (Fig. 7) .
• the tape is then advanced station 46 where it is heated. At the next stage 47 t lower thermal adhesive frame 18 is applied.
• the frame 18 is positioned to allow t portions 36 of the beam leads 34 to project beyond t frame 18.
• the lead frame 18 i brought into registry with the beam leads 34 with a vacu chuck 48.
• the heated beam leads 34 and frame 18 a pressed towards one another by moving the vacuum chuck 4 downwardly to bring the thermal adhesive into contact wit the beam leads and to further advance and press the fram 18 until it is flush with the lower surface 48 of the bea leads.
• the successive steps just described are shown i Figures 12B-12F.
• the foil tape is then advanced to the next station 51 wher the upper lead pack frame 22 is registered with the lowe lead pack frame.
• Figures 10-11 and is pressed downwardl as indicated by the arrow 52, Figure 11. This adheres th two frames together and imbeds the beam leads 34 betwee them.
• the lead support 29 is shown engaging the leads at location spaced from the frame.
• the metal foil is removed from the center 56, Figur 13, to leave the beam lead ends 36 cantilevered inwardl from the lead frame formed by the upper and lower lea frame portions 18 and 28 with the dimpled region space from the end of the lead as shown in Figure 14.
• the nex step 57, Figure 1A and Figure 15 is to apply an electric ally conductive thermal adhesive 58 to the lower side o the outwardly extending lead portions 34 and thereafte severing the leads from the foil tape, step 59, Figure 1A, to provide a lead pack comprising a frame with inwardl cantilevered lead portions 36 and outwardly extending lea portions 34 with an adhesive 58 on the underside of th outer end of the lead and a lead support and separator 2 as shown in Figure 16.
• the transport tape 1 includes a plurality of spaced windows 13 which are indexe by sprocket holes 14.
• the enlarged view of a portion 17-1 of the tape is shown in Figure 17.
• the tape includes plurality of test pads 61 connected by leads or lines 62 t lead ends 63 which extend to and are adjacent the edge o the window 13. If the transport tape is of electrical in sulating material such as mylar or polyamide, then the pad 61, leads 62, and ends 63 are formed by photoetching metal film carried by the tape.
• the tape is a stainless steel tape.
• the tape surfac is provided with a nonconductive adhesive layer to which metal film is applied and photo etched to define the leads
• the lead pack is place in the window 13, Figures 18 and 19, with the leads 3 overlapping the transport leads 63 and the conductiv thermal adhesive 58 therebetween and the assembly heated t thereby form electrical contact between the ends of th leads 34 and the ends 63 of leads 62 connected to test pad 61.
• the insertion of the lead pack in the window and con nection of the leads to transport leads is schematicall illustrated by the station 71.
• the lead pack is accuratel located and oriented by engaging the locating holes 35 i the lead frame tab 65.
• the next station 72 is where th cantilevered inner ends 36 of the lead pack leads ar bonded to the bonding pads of an associated chip 73 Figures 20 and 21.
• the lower lead fram portion 18 serves to guard against shorting of the lead 3 to the edge 75 of the semiconductor wafer 73.
• the end 3 of the lead may be bonded to the die by thermal compressio bonding, thermosonic bonding or ultrasonic bonding, or b other suitable bonding techniques with either single poin or gang bonding tools.
• the bonded assembly is then advanc ed to the next station 74 where electrical contact is mad to the test pads to electrically test semiconductor inte grated circuit 73 attached to the inner leads 36.
• the circuit can be packaged by molding a housin on the circuit using the frame as the mold dam, station 76
• the packaging can comprise a lower preforme packaged body 77, attached by thermal compression bondin as illustrated in Figures 22 and 23.
• the lower housing 7 is placed over the semiconductor die 73 and is presse against lower frame portion 18 while thermal energy i applied to melt the adhesive interface and to provide seal.
• the adhesive may adhere solely b pressure.
• the arrows 78 indicate pressure applied t provide a bonding force for the thermal adhesive bond t take place at the interface 79.
• the upper housing body 82 is applied by thermal compressio and/or adhesive bonding.
• the pressure is schematically illustrated by th arrows 83.
• the tab 65 and hole and slot 35 are used in th foregoing steps to maintain alignment of the housing wit respect to the leads by identifying the center and angular ity of the lead pattern.
• This same tab 65 and hole an slot 35 are used to locate the lead pack on the transport tape and again in the excise and lead form die assembly and again in application to the printed wiring board as an accurate placement means in match-up with a mating lead pattern or forming die, each adaptation being described hereafter.
• the encapsulation can be tested for seal and mechanical integrity followed b burn-in of the device at station 87, if desired.
• Final electric testing is performed at station 88 marking an coding the device package at station 89.
• th package is excised by cutting the leads 34 adjacent th leads 63 as shown in Figure 26. This step is also accu rately located by the hole and slot 35. Thereafter, th extending lead portions are bent as shown in Figure 27 t form feet 92, with the leads supported and spaced from on another by the frame 29.
• a packaged devic 95 formed in accordance with the present invention, i shown attached to a printed wiring board 96.
• the hole an slot 35 in tab 65 can be used for orientation.
• the trans port tape lead ends 63 can be cleaned to remove the elec tronically conductive adhesive and severed lead ends s that the transport and test tape can be reused.
• Th cleaning station is illustrated at 97.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Lead Frames For Integrated Circuits (AREA)
• Wire Bonding (AREA)

Applications Claiming Priority (2)

Publications (2)

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ID=23075611

Family Applications (1)

Country Status (3)

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Citations (5)

Family Cites Families (14)

• 1989
  • 1989-12-07 JP JP2501360A patent/JPH03505146A/ja active Pending
  • 1989-12-07 EP EP19900900714 patent/EP0406373A4/en not_active Withdrawn
  • 1989-12-07 WO PCT/US1989/005431 patent/WO1990006593A1/en not_active Application Discontinuation

Patent Citations (5)

Non-Patent Citations (4)

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