EP0295065A3 - Integrierte Schaltungshalbleiteranordnung, Verfahren zum Herstellen oder Schneiden derselben und Schneidesystem mit Energiebündel dafür - Google Patents
Integrierte Schaltungshalbleiteranordnung, Verfahren zum Herstellen oder Schneiden derselben und Schneidesystem mit Energiebündel dafür Download PDFInfo
- Publication number
- EP0295065A3 EP0295065A3 EP19880305199 EP88305199A EP0295065A3 EP 0295065 A3 EP0295065 A3 EP 0295065A3 EP 19880305199 EP19880305199 EP 19880305199 EP 88305199 A EP88305199 A EP 88305199A EP 0295065 A3 EP0295065 A3 EP 0295065A3
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- European Patent Office
- Prior art keywords
- same
- cutting
- semiconductor integrated
- integrated circuit
- circuit device
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- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/304—Controlling tubes by information coming from the objects or from the beam, e.g. correction signals
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Optics & Photonics (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62143065A JPS63307736A (ja) | 1987-06-10 | 1987-06-10 | イオンビ−ム加工方法 |
JP143065/87 | 1987-06-10 | ||
JP62181460A JPS6425441A (en) | 1987-07-21 | 1987-07-21 | Semiconductor integrated circuit device |
JP181460/87 | 1987-07-21 | ||
JP62187507A JP2735192B2 (ja) | 1987-07-29 | 1987-07-29 | エネルギービーム加工方法及びその装置 |
JP187507/87 | 1987-07-29 | ||
JP217030/87 | 1987-08-31 | ||
JP21703087A JPS6459933A (en) | 1987-08-31 | 1987-08-31 | Semiconductor device, and method and device for ion beam processing for production thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0295065A2 EP0295065A2 (de) | 1988-12-14 |
EP0295065A3 true EP0295065A3 (de) | 1991-07-03 |
Family
ID=27472497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19880305199 Withdrawn EP0295065A3 (de) | 1987-06-10 | 1988-06-08 | Integrierte Schaltungshalbleiteranordnung, Verfahren zum Herstellen oder Schneiden derselben und Schneidesystem mit Energiebündel dafür |
Country Status (1)
Country | Link |
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EP (1) | EP0295065A3 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0412185A1 (de) * | 1989-08-09 | 1991-02-13 | Siemens Aktiengesellschaft | Metallisierung mit Diffusionsbarriere für Halbleiterbauelemente |
US5089774A (en) * | 1989-12-26 | 1992-02-18 | Sharp Kabushiki Kaisha | Apparatus and a method for checking a semiconductor |
US6020746A (en) * | 1994-11-23 | 2000-02-01 | Intel Corporation | Method and apparatus for probing an integrated circuit through the back side of an integrated circuit die |
US6153891A (en) * | 1994-11-23 | 2000-11-28 | Intel Corporation | Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die |
US6159753A (en) * | 1996-12-20 | 2000-12-12 | Intel Corporation | Method and apparatus for editing an integrated circuit |
US5976980A (en) * | 1994-11-23 | 1999-11-02 | Intel Corporation | Method and apparatus providing a mechanical probe structure in an integrated circuit die |
US5952247A (en) * | 1994-11-23 | 1999-09-14 | Intel Corporation | Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate |
US5942805A (en) * | 1996-12-20 | 1999-08-24 | Intel Corporation | Fiducial for aligning an integrated circuit die |
US6309897B1 (en) | 1997-09-30 | 2001-10-30 | Intel Corporation | Method and apparatus providing a circuit edit structure through the back side of an integrated circuit die |
US5904486A (en) * | 1997-09-30 | 1999-05-18 | Intel Corporation | Method for performing a circuit edit through the back side of an integrated circuit die |
US6159754A (en) * | 1998-05-07 | 2000-12-12 | Intel Corporation | Method of making a circuit edit interconnect structure through the backside of an integrated circuit die |
DE10108924A1 (de) * | 2001-02-23 | 2002-09-05 | Infineon Technologies Ag | Wafer-Test- und Markierverfahren für Halbleiterbausteine mit Schmelzstrukturen |
US6692995B2 (en) | 2002-04-05 | 2004-02-17 | Intel Corporation | Physically deposited layer to electrically connect circuit edit connection targets |
US7973313B2 (en) | 2003-02-24 | 2011-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Thin film integrated circuit device, IC label, container comprising the thin film integrated circuit, manufacturing method of the thin film integrated circuit device, manufacturing method of the container, and management method of product having the container |
JP2008010818A (ja) * | 2006-06-01 | 2008-01-17 | Sumitomo Electric Ind Ltd | 基板、基板検査方法、素子および基板の製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985000468A1 (en) * | 1983-07-14 | 1985-01-31 | Advanced Micro Devices, Inc. | A semiconductor die having undedicated input/output cells |
-
1988
- 1988-06-08 EP EP19880305199 patent/EP0295065A3/de not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985000468A1 (en) * | 1983-07-14 | 1985-01-31 | Advanced Micro Devices, Inc. | A semiconductor die having undedicated input/output cells |
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EP0295065A2 (de) | 1988-12-14 |
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