EP0269692A1

EP0269692A1 - Monolithic channeling mask

Info

Publication number: EP0269692A1
Application number: EP19870903761
Authority: EP
Inventors: Gary M. Atkinson; John L. Bartelt
Original assignee: Hughes Aircraft Co
Current assignee: Raytheon Co
Priority date: 1986-05-27
Filing date: 1987-04-20
Publication date: 1988-06-08
Also published as: WO1987007400A3; WO1987007400A2; JPS63503425A

Abstract

Un masque (10) utile dans des techniques de lithographie par rayons X et par faisceaux ioniques masqués est préparé à partir d'une tranche polie (12) de silicium cristallin en ajoutant une couche supérieure de silicium (18) ayant un dopant de type p de taille ionique inférieure au silicium, en appliquant des couches de nitrure de silicium sur les surfaces supérieure (14) et inférieure (16), en formant par attaque chimique sélective une fenêtre (24) sur la surface inférieure (16) jusqu'à la couche (18) de silicum à dopage p pour former une membrane de silicium dopée en tension, à former par attaque chimique un motif dans la couche de nitrure de silicium (20) sur la surface supérieur (14), puis à former par attaque chimique un motif d'exposition traversant partiellement la membrane de silicium à dopage p. Le masque résultant est sensiblement monolithique et consiste essentiellement en une seule matière ne subissant pas de contraintes de distorsion internes significatives dues à une discordance d'expansion thermique pendant le chauffage et le refroidissement ultérieurs lorsqu'il est exposé aux faisceaux ioniques ou aux rayons X.A mask (10) useful in lithography techniques using X-rays and masked ion beams is prepared from a polished wafer (12) of crystalline silicon by adding an upper layer of silicon (18) having a p-type dopant. of ionic size smaller than silicon, by applying layers of silicon nitride on the upper (14) and lower (16) surfaces, by forming, by selective etching, a window (24) on the lower surface (16) until the layer (18) of p-doped silicon to form a silicon membrane doped in tension, to form by chemical etching a pattern in the layer of silicon nitride (20) on the upper surface (14), then to form by chemical etching an exposure pattern partially passing through the p-doped silicon membrane. The resulting mask is substantially monolithic and consists essentially of a single material which does not undergo significant internal distortion constraints due to a mismatch of thermal expansion during subsequent heating and cooling when exposed to ion beams or X-rays.

Description

MONOLITHIC CHANNELING MASK

BACKGROUND OF THE INVENTION

This invention relates to the preparation of integrated circuits, and, more particularly, to the preparation of integrated circuits by lithography techniques and fabrication of the masks used in the lithography.

Integrated circuits are electronic devices having multiple layers of various electronically active materials, processed so as to form discrete devices in the layers and in a number of adjacent layers. The integrated circuits are typically prepared using lithography techniques, wherein a layer of a semiconductor is deposited on a surface, a pattern is applied to the deposited layer by an appropriate technique, a portion of the layer defined by the applied pattern is removed by etching, and another layer of semiconductor material is deposited. Other steps such as the formation of external contacts may be interspersed with the repeated deposition, patterning and etching procedure. Through judicious design of the integrated circuits and careful attention to the fabrication techniques, large, complex circuits can be fabricated in very small areas by this approach.

A continuing trend in the field of integrated circuit technology is the reduction in size of the devices and the packing of higher densities of devices into single integrated circuits on a chip. Submicrometer devices are now fabricated with individual elements having sizes less than a micrometer. As the fundamental engineering for such very small devices is developed, the fabrication technology must also be found so that the fundamental advances can be used in large-scale integrated circuits.

One key obstacle that previously limited the size of elements of integrated circuits was the photolithography used to define patterns on the surfaces of deposited layers of semiconductor materials. When lithography using illuminating wavelengths in the visible or near-visible range is employed, the wave diffraction effects of the long wavelength radiation tend to blur the images and reduce the resolution of the lithography.

The problem arising from using radiation in the visible and near-visible range has been solved by using ion beam and x-ray lithography techniques, wherein the illuminating radiation used has a much shorter wavelength than light. Suitable resist, developing and etching techniques are available, and ion beam, electron beam, and x-ray lithography have been demonstrated for fabrication of integrated circuits with devices having submicron features.

In lithography techniques, a mask is prepared having an exposure pattern that is transparent to the illuminating radiation in areas corresponding to locations on the semiconductor to be exposed, and is opaque to the illuminating radiation in areas corresponding to those that are not to be exposed. The mask is placed over the semiconductor material to be patterned and etched, and the illuminating radiation exposes a resist layer on the surface of the semiconductor through the exposure pattern on the mask. The resist material is then developed and the pattern transferred to the semiconductor by etching.

The materials used in masks for photolithography were conventional light absorbing materials, which are unacceptable for masking ion beams or x-rays. Masks used in ion beam and x-ray lithography are made of materials that are radiation transparent or radiation absorbent in selected areas of masks that are themselves thin, on the order of at most about 1 to 2 microns in thickness.

The present masks for ion beam lithography use gold patterns of a thickness such that the ion beam is blocked and absorbed in the opaque portions of the mask, and with pattern openings therethrough as required. The gold patterns are supported on a thin silicon membrane, so that isolated absorbing areas of the mask are possible. The membrane is sufficiently thin that it transmits the incident ion beam or x-rays with minimum absorption and scattering. The process used to fabricate the masks is complex, with over 20 process steps, and has a limited yield of successfully fabricated masks.

The gold-absorber masks have certain limitations in use. Since the masks employ two different materials, gold and silicon, bonded together, the mask behaves much like a bimetallic strip such as a thermostat element due to the different thermal expansion parameters of the materials. The mask inherently displays internal thermal stresses after fabrication, and further internal thermal stresses develop in repeated heating and cooling cycles during their use in ion beam or x-ray lithography. The mask is repeatedly exposed to radiation in use, and the absorbed radiation heats the mask. The heating of the mask causes it to bend due to the differential thermal expansion, further warping the mask and distorting the pattern thereupon. Each component of warpage and distortion reduces the pattern resolution and pattern registry that can be achieved using the mask, thereby impairing the ability to fabricate small, precise devices using the mask.

Although the prior approach to ion beam mask structure and fabrication has been operable and has proved to be successful in reducing the scale of fabricated device elements for integrated circuits, the continuing advance of other technologies now have made mask design a limiting consideration in the ability to fabricate circuits of even smaller sizes. The problems just discussed must be resolved to achieve further advances in reducing the size of circuits produced by lithographic techniques. Moreover, it is problematic whether the complex process for producing the current ion beam and x-ray masks is sufficiently economic and productive to be competitive for the many masks needed in the commercial fabrication of complex integrated circuits having thousands of devices, and requiring tens of separate deposited layers, in a single chip.

Accordingly, there is a need for an improved structure for an ion beam and x-ray lithography mask, and a process for fabricating and using such an improved mask. The mask should reduce mask distortion during use and permit improved device element resolution. The fabrication process desirably would have a significantly reduced number and complexity of steps, so as to be more economical and have a higher yield of good masks. The present invention fulfills this need, and further provides related advantages. SUMMARY OF THE INVENTION

The present invention is embodied in a process for fabricating masks used in ion beam and x-ray lithography, the structure of such masks, and a process for using the improved masks. The masks of the invention are operable in lithography techniques using existing resist technology. They may be fabricated by applying processing steps that have been individually proved in other contexts. A reduced number of processing steps is required in fabricating the masks , and the critical patterning operation comes last, so that the yield of acceptable masks is improved. The masks themselves produce superior devices by lithography, because their reduced warpage due to lower internal stresses and absence of differential expansion stresses upon heating improves pattern registration accuracy and element resolution. In accordance with the present invention, a process for preparing a membrane channeling mask having an exposure pattern therein comprises the steps of furnishing a wafer of crystalline silicon having a channeling orientation; providing an epitaxial p-doped silicon layer at one surface of the wafer of silicon, the doping ion having an ionic size smaller than that of silicon; etching a window to the p-doped silicon layer through the undoped silicon wafer, the window having a lateral extent at least as large as the exposure pattern and extending through the thickness of the silicon wafer to the layer of p-doped silicon, to form a p-doped silicon membrane; and anisotropically etching the exposure pattern partially through the p-doped silicon membrane. Preferably, reactive ion etching or magnetron ion etching in a chlorine containing atmosphere. The crystallographic orientation of the wafer of silicon (and thence the p-doped silicon membrane that forms the portion of the mask through which the ion beam passes) is preferably (001) or (011), as defined by conventional Miller indices. The ion beam is channeled along the [001] or [011] directions in the crystal lattice with minimal absorbtion. Other orientations also exhibit the channeling effect and can be used.

The wafer of silicon is typically about 300 micrometers thick initially. A layer preferably about 2 to 3 micrometers thick having a p-type silicon dopant of a smaller ionic size than the silicon, to induce a small internal tensile stress in the finished mask, is added to the top surface of the wafer of silicon, preferably by epitaxial growth. A window is etched from the other surface of the silicon wafer to the p- doped silicon layer, preferably by depositing a window layer of silicon nitride and forming an opening of the lateral size of the window in the silicon nitride layer. Removal of the undoped silicon is conveniently accomplished through the opening in the silicon nitride layer with a selective anisotropic alkaline etch such as sodium hydroxide, potassium hydroxide or ethylenediamine pyrocatechol, that does not rapidly attack the p-doped silicon. The p-doped silicon membrane is therefore formed before any patterning and etching of the exposure pattern is undertaken, so that internal distortions are relaxed before the exposure pattern is formed. Distortion of the exposure pattern is thereby reduced, as compared with the alternative approach of window etching to form the membrane after the exposure pattern is etched.

The technique used to deposit silicon nitride on the bottom surface of the silicon piece readily deposits a silicon nitride layer on the top exposed surface, over the p-doped silicon layer. This top layer of silicon nitride is preferably present, to assist in subsequent etching steps, but is not absolutely necessary. At this stage, the mask is preferably mounted on a glass support ring having a coefficient of thermal expansion matched to that of the silicon wafer, for strength and ease of handling and to stablize the mask dimension .

The pattern of the mask is then transferred to the upper surface of the silicon nitride by any operable technique, with electron beam lithography being preferred. An electron-beam resist layer is applied to "the upper exposed surface and then the pattern is written onto the resist layer by a programmed electron beam. The electron beam resist is developed, and the optional top silicon nitride layer is removed down to the p-doped silicon layer, in the portions of the resist layer hhat are removed, as by magnetron assisted reactive ion etching. Additionally, magnetron ion etching is used to remove a portion of the thickness of the p-doped silicon to a reduced thickness of about 0.5 micrometers in those areas of the exposure pattern that are to be transparent to the ion beam or x-rays.

During later lithography procedures using the mask, the resulting thin regions of the p-doped silicon membrane transmit the portion of the ion beam or x-rays that is intended to be transmitted to the resist layer on the semiconductor, while the thicker regions of the p-doped silicon membrane absorb the portion of the beam that is to be masked. Optionally, a very thin emissive layer, such as a nickel-chromium alloy, can be added to the upper surface of the mask to radiate heat from the mask when in use.

More particularly, a process for preparing a membrane channeling mask having an exposure pattern therein comprises the steps of furnishing a wafer of crystalline silicon having a channeling orientation; growing an epitaxial p-doped silicon layer about 2 to about 3 micrometers thick on a top surface of the wafer of silicon, the dopant being selected from the group consisting of boron and aluminum; applying layers of silicon nitride to the top surface and to a bottom surface of the wafer of silicon, the layer on the bottom surface having an opening therethrough at least as large as the exposure pattern of the mask and the layer on the top surface overlying the p-doped silicon layer; etching away a portion of the silicon wafer through the opening in the silicon nitride layer on the bottom surface, the silicon being removed through its entire undoped thickness to expose the p-doped silicon layer, thereby forming a p-doped silicon membrane; attaching a support ring to the etched structure for strength and support, the support ring having a coefficient of thermal expansion matched to that of the silicon wafer; etching a pattern through the silicon nitride layer onto the top surface of the p-doped silicon membrane in the desired exposure pattern of the mask; and anisotropically etching the exposure pattern partially through the p-doped silicon membrane corresponding to the pattern etched through the silicon nitride layer on the top surface, the thickness of the remaining p-doped silicon layer in the etched exposure pattern being about 0.5 micrometers.

The masks produced by the present processes are unique, and no other masks are known which have their high resolution, low distortion, and perfection when used in ion beam and x-ray lithographic processes.

A process for applying a pattern to a substrate during masked ion beam lithography in integrated circuit fabrication comprises the steps of furnishing a monolithic p-doped silicon single crystal mask having a crystallographic channeling orientation and having an exposure pattern partially therethrough, the mask having no metallic absorber layer deposited thereupon; and exposing the substrate to radiation through the exposure pattern of the sil icon mask .

It will now be appreciated that the present invention provides a significant advance in the art. of fabrication of masks for use in ion beam and x-ray lithographic processes for the production of integrated circuits. The masks require fewer production steps and have a higher yield in production, reducing their cost. The masks also have improved performance due to lower internal stresses produced during fabrication, and particularly due to their greatly reduced tendency to warp and distort when repeatedly heated by the beam during exposure in the lithographic process. Other features and advantages of the present invention will be apparent from the following more detailed description, taken in conjunction with the accompanying drawing, which description illustrates, by way of example, the principles of the invention. BRIEF DESCRIPTION OF THE DRAWING

Figure 1 is a schematic flow diagram for a process for producing channeling masks, illustrating the structure of the mask at the different steps of the process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A brief description of the prior approach to fabricating ion beam lithographic masks is provided by way of background, and so that key differences can be later emphasized. The mask starts with a layer of silicon, preferably (001) orientation. Layers of silicon dioxide are grown on the top and bottom surfaces, and the top layer is etched. Boron is diffused into the top surface to form a layer of borosilicate glass on the top surface. The glass layer is etched from the top surface back to the region of high boron conctentration.

A resist layer is applied to the bottom surface of the mask over the silicon dioxide layer. A window is etched in the silicon dioxide layer using the resist layer. A 500

Angstrom layer of chromium and a 7000 Angstrom layer of gold are deposited on the top of the boron layer. A resist layer is applied and then the exposure pattern is formed in the gold. The gold exposed by the pattern is removed by ion beam milling, and a 200 Angstrom layer of chromium is applied. This critical and costly step of pattern development in the gold is an intermediate step, with further process steps to follow. If any of the later process steps fails, then the effort expended in the pattern formation step is lost. Next, the silicon membrane is thinned to the boron doped layer by etching from the back side through the window previously formed. The chromium and silicon dioxide are removed by chemical etching, and the mask is mounted to complete the process.

Implementation of this process requires some 22 different process steps. The critical pattern formation is followed by other steps, increasing the chances that the expenditures made in the pattern formation step will be lost by failures in succeeding steps and increasing the possibility of distortion of the pattern during subsequent steps, as by stress relaxation. The mask itself has imperfections and stresses upon fabrication. Because of its bimaterial construction of gold and silicon, the different thermal expansion coefficients cause the mask to warp and distort when repeatedly heated and cooled in use.

In a preferred embodiment of the present invention for producing a mask 10, a silicon single crystal wafer 12 of thickness about 300 micrometers is furnished. The silicon wafer 12 should have a crystallographic orientation that permits channeling of the ion beam along the crystallographic through-thickness direction. The (001) and (011) crystallographic orientations and the corresponding [001] and [011] directions are known to have this channeling capability and are therefore preferred. Other orientations and directions meeting the requirement are also operable. The thickness of the silicon wafer 12 is not critical, inasmuch as all portions that might lie within the ion beam pattern, except for the p-doped portion, are removed. Silicon single crystal slices of about 2 inch diameter and 300 micrometers thickness are typically used, to permit handling and because of ready availability.

The silicon wafer 12 is provided as a platelike slice of much larger lateral extent than thickness. The silicon wafer 12 can be described as having a top surface 14 and a bottom surface 16, and these terms will be used to provide a frame of reference for the fabrication steps illustrated in Figure 1. A layer 18 of p-doped silicon is formed on the top surface of the silicon piece by any appropriate technique such as epitaxial growth. The concentration of the dopant is preferably about 1 to 4 x 10²⁰ ions per cubic centimeter. The p-doped layer IS has three important characteristics. First, it forms the actual mask material and therefore must have the proper absorbing and channeling characteristics with minimum distortion. Second, the presence of the smaller dopant ions induces tensile prestress in the layer 18 which is beneficial to retaining the pattern in the finished mask during heating by the ion beam in lithographic processes. Third, it acts as an etch stop for etchants used in the process.

The layer of p-doped silicon should be about 2-3 micrometers thick as deposited. This thickness is sufficient to absorb the ion beam energy when the mask is later used in lithography. The thickness is reduced in a later process step to about 0.5 micrometers in the exposure pattern areas that are to transmit the ion beam.

The dopant for the silicon is any P-type dopant whose ionic size in silicon is less than that of the silicon itself. Boron is preferred, because of its small size and established doping technology. Other p-type dopants such as aluminum are also thought to be operable.

A layer of silicon nitride 20 about 500 Angstroms thick is applied over the layer of p-doped silicon 18 lying on top of the silicon wafer 12, and another layer of silicon nitride 22 is applied to the bottom of the wafer 12. The silicon nitride layers act as patterning elements to allow removal of material from the underlying layers and substrate.

A large window 24 is formed on the bottom surface of the silicon wafer 12. An opening through the layer of silicon nitride 22 is first etched using carbon tetrafluoride reactive ion etching. This opening is larger in lateral extent than the exposure pattern that is later developed in the p-doped silicon wafer. Through the opening in the silicon nitride layer 22 on the bottom of the silicon wafer 12, the deep window 24 is etched through the thickness of the silicon wafer 12 to expose the p-doped silicon layer 14, which acts as an etch stop, using, for example, 10 N concentration sodium hydroxide solution for about 2-1/2 hours. The deep window 24 is thereby formed in the silicon wafer 12 below a portion of the p-doped silicon layer 18 so that the ion beam can pass therethrough when the mask is used in li thography processes. The exposed p-doped silicon layer 14 becomes a prestressed membrane into which the exposure pattern is later etched. The remaining portion of the silicon wafer 12 acts as a toroidal support to support and hold the remainder of the mask for processing and in use. A glass mounting ring 26 is also preferably attached to the remaining toroidal section of the silicon piece 12 to provide additional support and strength. The glass ring has a coefficient of thermal expansion matched to that of the silicon wafer, to minimize thermal expansion mismatch strains and stresses between the two. A layer of electron beam resist material 28 is applied over the top layer of silicon nitride 20 and thence overlying the layer of p-doped silicon 18. A pattern is written into the resist by an electron beam programmed with the desired exposure pattern of the mask 10. The resist is then developed and the exposure pattern transferred to the top silicon nitride layer 20 using standard techniques.

The exposure pattern in the silicon nitride layer 20 is transferred to the p-doped silicon layer 18 using magnetron ion etching in a CI2/NF3 atmosphere. The magnetron ion etching is continued as necessary to thin the p-doped silicon layer 18 to a sufficiently small thickness that an ion beam used in lithography is channeled through the etched thickness with minimally small and acceptable absorption. The thickness depends upon the energy of the ion beam that is to be used in lithography, but is typically about 0.5 micrometers in a mask to be used with an ion beam having an energy of 225 KEV (thousand electron volts). It is known that about 100 KEV of energy of the ion beam is .lost for each 1 micrometer thickness of the p-doped silicon layer 18. The total thickness of the p-doped silicon layer 18, about 2-3 micrometers, is sufficient to absorb nearly all of the 225 KEV ion beam. On the other hand, only about 50 KEV of beam energy is lost in the 0.5 micrometer thickness of p-doped silicon in the thinned regions of the exposure pattern, so that substantially all of the ion beam is transmitted by channeling through this portion, at a slightly reduced energy of about 175 KEV.

The silicon nitride top and bottom layers 20 and 22 are then removed by etching in dilute hydrofluoric acid, and the mask is ready for use. During the preceding process steps, the thickness of the silicon nitride layers is reduced to about 200 Angstroms, and it is believed that these layers could be left in place without detrimental effects on performance of the mask. Such a thin layer has so little strength that it does not have a significantly detrimental effect on the performance of the mask during use through the creation of thermal stresses. A thin layer of a thermally emissive material such as an alloy of nickel and chromium may be added to the top surface of the mask to increase its heat emission during ion beam or x-ray lithography, when the mask is heated. Such a layer would be very thin, as about 200 Angstroms, and also would have little strength. Thus, the presence of very thin layers of silicon nitride or an emissive material would be within the concept of a substantially monolithic mask of a single material, because such layers would not have sufficient strength to create significant stresses caused by differences in coefficients of thermal expansion.

As is apparent, the mask region bearing the exposure pattern is substantially monolithic, being formed of a single material, the p-doped silicon layer or membrane. The membrane is formed by etching away the underlying portion of the silicon wafer prior to patterning, so that any stresses resulting from the removal of the silicon wafer are relaxed before the exposure pattern is etched into the p-doped silicon membrane. This approach reduces the tendency of the mask and the exposure pattern to produce a distorted image during lithography. The in-plane distortion in use has been calculated to be about half that of gold/silicon masks made by the prior approach. The mask of the present invention also has a significantly higher yield in mask fabrication than experienced with the prior gold/silicon masks, due to the reduced number of process steps and the placing of the pattern definition at the end of the process.

Although a particular embodiment of the invention has been described in detail for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)

(51) International Patent Classification 4 (11) International Publication Number: WO 87/ 074 G03F 1/00 A3 (43) International Publication Date: 3 December 1987 (03.12.

(21) International Application Number: PCT/US87/00878

(81) Designated States: AT (European patent), BE (Eu

(22) International Filing Date: 20 April 1987 (20.04.87) pean patent), CH (European patent), DE (Europe patent), FR (European patent), GB (European tent), IT (European patent), JP, KR, LU (Europe

(31) Priority Application Number: 867,659 patent), NL (European patent), SE (European tent).

(32) Priority Date: 27 May 1986 (27.05.86)

(33) Priority Country: . US Published

With international search report.

(71) Applicant: HUGHES AIRCRAFT COMPANY [US/ (88) Date of publication of the international search report:

US]; 7200 Hughes Terrace, Los Angeles, CA 90045-0066 (US). 7 April 1988 (07.04.8

(72) Inventors: ATKINSON, Gary, M. ; 11865 Rochester

Avenue, Apt. 5, Los Angeles, CA 90025 (US). BAR- TELT, John, L. ; 1090 Waverly Heights Drive, Thousand Oaks, CA 91360 (US).

(74) Agents: DENSON-LOW, Wanda, K. et al.; Hughes Aircraft Company, Post Office Box 45066, Bldg. Cl, M.S. A126, Los Angeles, CA 90045-0066 (US).

(54) Title: MONOLITHIC CHANNELING MASK

(57) Abstract

A mask (10) useful in masked ion beam and x-ray lithography is prepared from a polished wafer (12) of crystalline silicon by adding a top layer of silicon (18) having a p-type dopant of an ionic size less than silicon, applying silicon nitride layers to the top (14) and bottom (16) surfaces, selectively etching a window (24) from the bottom surface (16) up to the layer (18) of p-doped silicon to form a doped silicon membrane in tension, etching a pattern in the layer of silicon nitride (20) on the top surface (14), and then etching an exposure pattern partially through the membrane of p-doped silicon. The resulting mask is substantially monolithic, consisting primarily of a single material that does not experience significant internal distortion stresses due to thermal expansion mismatch during later heating and cooling when exposed to an ion beam or x-rays.

^^

Claims

CLAIMSWhat is claimed is:

1. A process for preparing a membrane channeling mask having an exposure pattern therein, comprising the steps of: furnishing a wafer of crystalline silicon having a channeling orientation; providing an epitaxial p-doped silicon layer at one surface of the wafer of silicon, the doping ion having an ionic size smaller than that of silicon; etching a window to the p-doped silicon layer through the undoped silicon wafer, the window having a lateral extent at least as large as the exposure pattern and extending through the thickness of the silicon wafer to the layer of p-doped silicon, to form a p- doped silicon membrane; anisotropically etching the exposure pattern partially through the p-doped silicon membrane.

2. The process of Claim 1, wherein the wafer of silicon has a crystallographic orientation of (001).

3. The process of Claim 1, wherein the initial thickness of the wafer of silicon is about 300 micrometers.

4. The process of Claim 1, wherein the layer of p-doped silicon is doped with boron ions.

5. The process of Claim 1, wherein the layer of p-doped silicon is doped with aluminum ions.

6. The process of Claim 1, wherein the thickness of the layer of p-doped silicon on the top surface of the wafer of silicon is from about 2 to about 3 micrometers .

7. The process of Claim 1, including the further step of mountig the mask on a mounting ring to add structural strength.

8. The process of Claim 19, wherein either the first or second masking layer is silicon nitride is about 500 Angstroms thick.

9. The process of Claim 1, wherein the undoped silicon is etched away with a solution selected from the group consisting of sodium hydroxide solution, potassium hydroxide solution, and ethylenediamine pyrocatechol solution.

10. The process of Claim 1, including the further step of applying an emissive layer to the upper surface of the mask.

11. The process of Claim 1, wherein the pattern in the layer of silicon nitride on the top surface is prepared by applying an electron beam resist material to the silicon nitride, exposing a pattern by electron beam lithography, developing the pattern in the resist material, and etching away the silicon nitride.

12. The process of Claim 1, wherein the thickness of the p-doped silicon in the etched portions of the exposure pattern is about 0.5 micrometers.

13. A mask prepared by the process of Claim 1.

14. A process for preparing a membrane channeling mask having an exposure pattern therein, comprising the steps of: furnishing a wafer of crystalline silicon having a channeling orientation; growing an epitaxial p-doped silicon layer about 2 to about 3 micrometers thick on a top surface of the wafer of silicon, the dopant being selected from the group consisting of boron and aluminum; applying layers of silicon nitride to the top surface and to a bottom surface of the wafer of silicon, the layer on the bottom surface having an opening therethrough at least as large on the top surface overlying the p-doped silicon layer; etching away a portion of the silicon wafer through the opening in the silicon nitride layer on the bottom surface, the silicon being removed through its entire undoped thickness to expose the p-doped silicon layer, thereby forming a p-doped silicon membrane; attaching a support ring to the etched structure for strength and support, the support ring having a coefficient of thermal expansion matched to that of the silicon wafer; etching a pattern through the silicon nitride layer onto the top surface of the p-doped silicon membrane in the desired exposure pattern of the mask; and etching the exposure pattern partially through the p-doped silicon membrane corresponding to the pattern etched through the silicon nitride layer on the top surface, the thickness of the remaining p-doped silicon layer in the etched exposure pattern being about 0.5 micrometers.

15. A mask prepared by the process of Claim 14.

16. A process for applying a pattern to a substrate during masked ion beam lithography in integrated circuit fabrication, comprising the steps of: furnishing a monolithic p-doped silicon single crystal mask having a channeling orientation and having an exposure pattern partially therethrough, the mask having no metallic absorber layer deposited thereupon; and exposing the substrate to radiation through the exposure pattern of the silicon mask.

17. An integrated circuit prepared by the process of Claim 16.

18. The anisotropic etching of Claim 1 is reactive ion etching or magnetron ion etching in a substantially chlorine containing atmosphere.

19. The process of Claim 1 wherein a first masking layer, used to define the exposure pattern is on the top surface of the wafer and a second masking layer, used to define the membrane window is on the bottom surface of the wafer.