EP0161319A1 - Appareil de commande d'ecriture et de lecture en relation a une memoire graphique - Google Patents

Appareil de commande d'ecriture et de lecture en relation a une memoire graphique Download PDF

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Publication number
EP0161319A1
EP0161319A1 EP84903820A EP84903820A EP0161319A1 EP 0161319 A1 EP0161319 A1 EP 0161319A1 EP 84903820 A EP84903820 A EP 84903820A EP 84903820 A EP84903820 A EP 84903820A EP 0161319 A1 EP0161319 A1 EP 0161319A1
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EP
European Patent Office
Prior art keywords
bit
graphic
cpu
data
rams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84903820A
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German (de)
English (en)
Other versions
EP0161319B1 (fr
EP0161319A4 (fr
Inventor
Yoshiaki Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
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Fanuc Corp
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Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Publication of EP0161319A1 publication Critical patent/EP0161319A1/fr
Publication of EP0161319A4 publication Critical patent/EP0161319A4/fr
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Publication of EP0161319B1 publication Critical patent/EP0161319B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/022—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using memory planes

Definitions

  • the present invention relates to a write/read control unit for a graphic memories in a color graphic display.
  • the method 1) is small in the amount of hardware required but needs at least two cycles of operation of the CPU for the one-bit write, and hence has the defect of low processing speed.
  • the method 2) permits the modification of one bit in one cycle of the CPU but requires very complex hardware, and hence is costly.
  • An object of the present invention is to make it possible to modify one bit in one cycle of the CPU simply by the additional provision of a small amount of hardware.
  • the graphic memory write/read control unit writes data, bit by bit, into graphic memories for red, green and blue pictures, each having a capacity of N x M bits, and reads out data therefrom in units of M bits.
  • the graphic memories for red, green and blue pictures each comprise an RAM group of an M-bit output which includes M RAMs each having a one-bit output and a 1 x N bit capacity.
  • the graphic memories for red, green and blue pictures are assigned the same address spacer, and different one-bit data lines of a data bus of the CPU are connected to all the RAMs of the graphic memories for red, green and blue pictures.
  • the aforementioned bitwise data write is effected specifying one bit of each RAM of each graphic memory by a CPU address and by sending a write signal to an arbitrary one of the M RAMs by a part of the CPU address.
  • Fig. 1 is a block diagram illustrating the principal part of an example of the hardware structure of the write/ read control unit according to the present invention
  • Figs. 2 and 3 are diagrams showing the relationships between respective areas of RAMs 2 0 to 2 7 and display positions on the display screen
  • Fig. 4 is a diagram showing examples of signal waveform occurring at respective parts in Fig. 1
  • Fig. 5 is a folwchart showing an example of processing by a CPU 8 for writing graphic data into graphic memories 1R, 1G and 1B
  • Fig. 6 is a diagram showing an example of the data format of the CPU
  • Fig. 7 is a block diagram illustrating an embodiment of a timing gererator 14.
  • reference numeral 1R indicates a graphic memory for a red picture
  • 1G a graphic memory for a green picture
  • 1B a graphic memory for a blue color, each of which is provided with eight RAMs 2 0 to 2 7 each having a capacity of 1 x N bits.
  • These graphic memories have the same address space.
  • Fig. 1 only the graphic memory 1R for a red color picture is shown to have the eight RAMs 2 0 to 2 - for convenience sake, but the other graphic memories 1R and 1B also have the eight RAMs.
  • the outputs of the graphic memories 1R, 1G and 1B are eight-bit, that is, one bit is o obtained from each of the RAMs 2 0 to 2 7 and a total of eight bits are set in each of shift registers 3R, 3G and 3B. For example, if the respective output bits of the RAMs 2 0 to 2 7 are numbered, as shown in Fig. 2, then each of a total of 8 x N bits corresponds, on a display screen 4, to one of areas shown in Fig. 3, for instance.
  • Bits (for example, 0 to 7, 8 to 15, etc.) at the same locations in the RAMs 2 0 to 2 7 are read out by one of addresses for display which are applied via multiplexer 6 from a CRT controller 5, and the eight bits are simultaneously set in each of the shift registers 3R, 3G and 3B and then input as red, green and blue video signals, in the form of serial data, by a dot clock dc (the frequency of which is eight times higher than that of a clock for counting up a display address counter) from the CRT controller 5, via AND circuits 7R, 7G and 7B into a CPU not shown.
  • dc the frequency of which is eight times higher than that of a clock for counting up a display address counter
  • a signal f input into each of the AND circuits 7R, 7G and 7B from the CRT controller 5 is a signal which is a "0" only during the horizontal flyback period and is a gate signal which causes the red, green and blue video signals to be output only during the display period.
  • the data input to the RAMs 2 0 to 2 7 is effected by zeroth, first and second biys (a0), (a l ) and (a 2 ) of a data bus 9 of a CPU 8 in connection with the graphic memories 1R, 1G and 1B for red, green and blue pictures, respectively. Namely, in any of the graphic memories, only a rewrite of one-bit data is effected in one cycle of operation of the CPU 8.
  • Reference numerals 10R, 10G and 10B indicate drivers.
  • Addressing and sending of a write signal for writing one-bit data from the CPU 8 into the RAMs 2 0 to 2 7 are carried out in the following manner: Of a 16-bit address bus 11 of the CPU 8, zeroth to second bits (a 0 , a 1 and a2), i.e. a total of three bits, are provided to a RAM selector 12 and, for example, 10 bits of the remaining bits are applied to the multiplexer 6. The addressing of each graphic memory is effected by the CPU address that is input via the multiplexer 6.
  • the RAM selector 12 is further supplied with a signal d from an address decoder 13 and a signal c from a timing generator 14, and the AND signal of the signasls d and c is provided on any one of eight output lines 12 0 to 12 7 . It is dependent upon the contents of the three low-order bits (a 2 , a 1 and a o ) to which output line the above AND signal is output.
  • the eight output lines 12 0 to 12 7 are each connected to one of write terminals of the RAMs 2 0 to 2 7 of each of the graphic memories 1R, 1G and 1B.
  • the address decoder 13 decodes address information on the address bus 11 and makes the signal d a "1" when the CPU is to access the graphic memories 1R, 1G and 1B, and makes a signal e a "1" when the CPU is to access the CRT controller 5.
  • the address decoder 13 can be constituted by an AND circuit which, assuming that the address space of each of the graphic memories 1R, 1G and 1B is F0000 to FFFF, makes the signal d a "1" when four bits of addresses al6 to a19 of the CPU all go to "is”, and an AND circuit which makes the signal e a "1" when the address space of the CRT controller is accessed.
  • the timing generator 14 when receiving the write signal from the CPU 8, makes the signal c a "1" in tne write cycle of the RAMs 2 0 ro 2 7 immediately thereafter. Furthermore, the timing generator 14 outputs a signal a to the multiplexer 6 and a signal b to the shift registers 3R, 3G and 3B.
  • the signal a is to make a distinction between the cycle of reading out data from the graphic memories 1R, 1G and 1B and the cycle of writing thereinto data from the CPU 8, and by this signal a, the output of the multiplexer 6 is switched between the side of the address bus 9 of the CPU and the side of the CRT controller 5.
  • a signal b is a strobe signal by which eight-git data read out of the graphic memories 1R, 1G and 1B is latched in the shift registers 3R, 3G and 3B, respectively.
  • the timing generator 14 can be arranged, for instance, as shown in Fig 7.
  • an octal counter 70 is counted up by the dot clock dc and outputs Q 1 , Q 2 and Q 3 of its three low-orqer bits are taken out.
  • the outputs Q 1 to Q 3 are provided to an AND circuit 71, the output of which is used as the signal b.
  • the signal Q 3 becomes the signal a.
  • the dot clock dc is applied to the clock terminals of flip-flops 73 and 74 as well.
  • the write signal and the output of the AND circuit 71 are ANDed by an.AND circuit 72, the output of which is input to the set terminal S of the flip-flop 73.
  • the output Q of the flop-flop 73 is connected to the set terminal S of the flip-flop 74, the inverting output Q of the flip-flop 73 is connected to the reset terminal R of the flip-flop 74 and the output Q of the flip-flop 74 is connected to the reset terminal R of the flip-flop 73.
  • the output Q of the flip-flop 74 is used as the signal c.
  • Fig. 4 shows timing charts of the dot clock which serves as shift pulses of the shift registers 3R, 3G and 3B, a word clock for counting up the display address, the output of the multiplexer 6, the input to each of the graphic memories 1R, 1G and 1B, the output of each of the graphic memories 1R, 1G and 1B, the signals a, b and c and the write signal from the CPU 8.
  • the contents of the graphic memories 1R, 1G and 1B are read out by steps of eight bits and the write cycle occurs in the interval between the read cycles.
  • Fig. 5 is a flowchart showing an example of processing by the CPU 8 for writing graphic data into the graphic memories 1R, 1G and 1B.
  • the creation of a graphic form starts with deciding the color in which the graphic form is to be cisplayed.
  • the following information is stored in three low-order bits of an eight-bit register such as an internal register of the CPU. That is, as shown in Fig. 6, red information is set in the least significant bit a 0 , green information in the next bit a 1 and blue information in the next bit a 2 .
  • the data of the above register is written into an address of the concerned one of the RAMs 2 0 to 2 7 .
  • a write signal is produced, as shown in Fig. 4, after which the three low-order bits of the CPU address are made, for example, (0, 0, 1) so as to select the output line 12 1 and the address being applied to the multiplexer 6 is set so that the second area of the RAM 2 1 is selected.
  • data (00000001) is provided on the data bus 9.
  • the multiplexer 6 when the multiplexer 6 is changed over by the signal a, the contents of the graphic memories 1R, 1G and 1B are read out by steps of eight bits and the data of the RAM 2 1 is read out and displayed in at least one scanning period of the display screen.
  • a write/read control unit which writes, bit by bit, data into graphic memories for red, green and blue pictures, each having a capacity of N x M bits, and reads out therefrom the data by steps of M bits
  • the graphic memories for red, green and blue pictures are each formed by a RAM group of an M-bit output which includes M RAMs each having a one-bit output and a 1 x N bit capacity and since the graphic memories for red, green and blue pictures are assigned the same address space, it is possible to specify, by one addressing from a CPU, eight bits of the same addresses of the graphic memories for red, green and blue pictures.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)

Abstract

Appareil de commande d'écriture de lecture en relation à des mémoires graphiques (1R, 1G, 1B) pour un écran rouge, un écran vert et un écran bleu, respectivement, chacune des mémoires graphiques ayant une capacité de N x M bits. L'appareil fonctionne de manière que les données sont écrites dans les mémoires graphiques (1R, 1G, 1B) bit par bit et sont lues et extraites des mémoires dans des unités de M bits. L'appareil est capable de modifier un bit par cycle d'une unité centrale de traitement (CPU) (8) avec un nombre réduit d'éléments machine. Chacune des mémoires graphiques (1R, 1G, 1B) est constituée par un groupe RAM de sortie à M-bits consistant en des RAMs (2o à 27) de sortie à M 1-bits, ayant chacune une capacité de 1 x N bits. En outre, le même volume d'adresses est affecté aux mémoires graphiques (1R, 1G, 1B), et des lignes de données 1-bit d'un bus de données (9) de l'unité centrale CPU (8) sont connectées respectivement à toutes les RAMs (2o à 27) dans chacune des mémoires graphiques (1R, 1G, 1B). L'écriture des données qui s'effectue bit par bit est mise en oeuvre de manière qu'un bit de chacune des RAMs (2o à 27) dans chacune des mémoires graphiques (1R, 1G, 1B) est spécifié par les adresses du CPU, et un signal d'écriture est envoyé aux M RAMs (20 à 27) désirées avec une partie de l'adresse CPU.
EP84903820A 1983-10-25 1984-10-22 Appareil de commande d'ecriture et de lecture en relation a une memoire graphique Expired EP0161319B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58199571A JPS6090387A (ja) 1983-10-25 1983-10-25 グラフイツクメモリの書込み読出し制御装置
JP199571/83 1983-10-25

Publications (3)

Publication Number Publication Date
EP0161319A1 true EP0161319A1 (fr) 1985-11-21
EP0161319A4 EP0161319A4 (fr) 1986-04-02
EP0161319B1 EP0161319B1 (fr) 1989-11-02

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Application Number Title Priority Date Filing Date
EP84903820A Expired EP0161319B1 (fr) 1983-10-25 1984-10-22 Appareil de commande d'ecriture et de lecture en relation a une memoire graphique

Country Status (4)

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EP (1) EP0161319B1 (fr)
JP (1) JPS6090387A (fr)
DE (1) DE3480363D1 (fr)
WO (1) WO1985002050A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6067989A (ja) * 1983-09-26 1985-04-18 株式会社日立製作所 画像表示装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329033A (en) * 1976-08-31 1978-03-17 Victor Co Of Japan Ltd Display unit
EP0085480A2 (fr) * 1982-01-13 1983-08-10 Europel Systems (Electronics) Ltd. Systèmes d'affichage vidéo

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3141882A1 (de) * 1981-10-22 1983-05-05 Agfa-Gevaert Ag, 5090 Leverkusen Dynamische schreib- und lesespeichervorrichtung
JPH05329033A (ja) * 1992-06-02 1993-12-14 Toyota Motor Corp ロッドの伸縮移動拘束装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5329033A (en) * 1976-08-31 1978-03-17 Victor Co Of Japan Ltd Display unit
EP0085480A2 (fr) * 1982-01-13 1983-08-10 Europel Systems (Electronics) Ltd. Systèmes d'affichage vidéo

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8502050A1 *

Also Published As

Publication number Publication date
JPS6090387A (ja) 1985-05-21
EP0161319B1 (fr) 1989-11-02
DE3480363D1 (en) 1989-12-07
WO1985002050A1 (fr) 1985-05-09
EP0161319A4 (fr) 1986-04-02

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