EP0085480A2 - Systèmes d'affichage vidéo - Google Patents
Systèmes d'affichage vidéo Download PDFInfo
- Publication number
- EP0085480A2 EP0085480A2 EP83300104A EP83300104A EP0085480A2 EP 0085480 A2 EP0085480 A2 EP 0085480A2 EP 83300104 A EP83300104 A EP 83300104A EP 83300104 A EP83300104 A EP 83300104A EP 0085480 A2 EP0085480 A2 EP 0085480A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- video
- colour
- display
- data
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
Definitions
- the present invention relates to video display systems and more particularly but not exclusively to video displays for amusement or games.
- the present invention provides a video display system including storage means for storing data to be displayed, a raster scan display for display of the data, a video controller for selection in a single clock pulse period, the addresses in said storage means of a plurality of dots to be displayed on said raster scan display at positions determined by said video controller, and including a parallel to serial converter to provide data on each dot sequentially to the raster scan display.
- the colour information is transferred during one part of each clock pulse cycle the other part of the clock pulse cycle being allowed for access to the system by microprocessor control means.
- the number of dots to be displayed in each plurality is four or eight.
- a method of displaying video data on a raster scan cathode ray tube including storing the video data in a digital form in a random access memory, transferring the digital video data from said random access memory to a video memory, in which a display is stored as a series of colour numbers corresponding to dots on the raster scan cathode ray tube, under the control of a programme sequence stored in said random access memory, such that the video colour data stored in said video memory is accessible under the control of a video controller to be output to a plurality of colour look up random access memories which control digital to analogue circuits for display of the video data on the cathode ray tube.
- the video display system described hereinbelow is intended for use with a Raster scan cathode ray tube system and permits vector colour graphics on the screen of a Raster cathode ray tube.
- control system comprises a 16 bit processor 10 which is connected to a main data bus 12 and a main address bus 14.
- a video controller 16 Connected to the data bus 12 is a video controller 16 and connected to the video controller 16 is a multiplexer 18 controlled by the clock generator 23.
- the main video random access memory 20 comprising 16 x 64K (32 x 64K for higher resolution) bit RAM is connected to the multiplexer 18.
- a clock generator and controlled circuit 23 is used to provide the clock signals and control signals on outputs o/p shown in greater detail in Figure 2.
- the outputs of the 16 RAM'S 20 are connected to four shift registers 24 which store the outputs.
- the output of these shift registers 24 are connected to a multiplexer 26 which multiplexes either the video data or part of the main address bus 14 onto the address lines of the three colour look-up RAMS 28, 30 and 32, depending upon whether the circuit is in display mode or colour look-up RAM update mode as determined by the programme running from the processor.
- each colour look-up RAM is fed via respective digital to analogue converters 34, 36, 38 to the red green and blue colour guns of the video display 39 (see Figure 2).
- the outputs of the 16 RAMS 20 are also connected to a latch 22 which optionally includes a multiplexer/selector which can pass the video data onto the data bus 12.
- Sound generation for the display is achieved using a sound generator circuit 40 connected to the main data bus 12.
- the fast 16 bit Processor 10 is used tc permit the video data to be moved in the shortest possible time.
- a slower 8 bit version is possible which moves the data more slowly.
- Another version provides for each pixel to occupy 4 bits of a byte (8 bits) in the processor address map in which case two pixels are moved with each 16 bit word data move or an individual pixel is moved with a byte data move.
- the Processor used is the 68000 in a preferred embodiment.
- each group of four dots are described herein as being horizontally adjacent it will be understood that they could be vertically adjacent. Whether the dots are horizontally or vertically adjacent depends upon the physical orientation of the display CRT (vertical or horizontal), the orientation of Raster scan which drives the CRT, or the order of the address lines between the video controller 16 and the multiplexer 18 in conjunction with their interpretation by the programme running on the processor, i.e., which part of the screen the programme considers to be top/bottom and left/right.
- the video controller 16 is used to generate the address of the next 4 dots to be displayed. This dot address is fed via the Multiplexer 18 to the video RAM 20 (16 off 64K dynamic RAMS).
- the Multiplexer 18 provides the ability to address the video RAM 20 from the Processor Address Bus 14.
- the 16 bits of data out from the video RAM 20 are fed into the four 4 bit shift registers 24, which are clocked in parallel to provide a 4 bit wide colour number for each individual dot.
- Each video RAM 20 data access by the video controller 16 provides data on 4 dots, horizontally adjacent.
- a version offering twice the horizontal resolution would use 32 RAM devices in the video RAM which would still be clocked into four shift registers but each shift register would now be eight bits long and be shifted at twice the rate.
- a version offering twice the vertical resolution could use 256K RAMS.
- the 4 bits defining the dot colour are fed via a Multiplexer 26 to the 16 location 12 bit wide fast colour look-up RAMS 28, 30, 32.
- the Address Multiplexer 26 provides the ability to address this RAM from the Processor Address Bus 14.
- the colour look-up RAMS 28, 30, 32 provide a look-up table to define the actual colour.
- the 4 bits from the video RAM 20 addressing one of 16 locations, each of which contains 12 bits of data, which are used in 3 groups of 4 to drive fast Digital to Analog Converters 34, 36, 38.
- further bits may be used which can correspondingly increase the size of the colour look-up RAM and the number of shift registers but permit a greater number of colours to be selected i.e. 5 bits allows 32 colour locations.
- the output of the Digital to Analog Converters drives the red, green and blue guns of the television tube, so that for any particular colour code, each of the 3 guns can be set to 1 of 1 6 predetermined levels, giving 4096 possible colours.
- a general purpose asynchronous character serial output is provided.
- a custom chip is used for the clock generator and control circuit 23 (Uncommitted Logic Array) to generate all of the timing signals for the video RAM 20, and in addition address decoding for the programme memory, data memory and input/output circuits 44, 46, 48, 50.
- the clock generator and control circuit 23 Uncommitted Logic Array
- EPROM or ROM Program Memory is included in RAM 42, with options for 32K bit, 64K bit or 128K bit EPROMS.
- a convenient linking arrangement is used, whereby all required signals are brought to a dual in-line header, and an option socket plugged onto the header determines which type of EPROM is to be configured.
- the programme memory consists typically of EPROM or ROM memory chips and will contain the computer programme which is executed by the processor to control operation of the complete system.
- This memory contains all information to define the sequence and pattern of all accesses to the random access memory and the video memory. To change the function and application for the use of this circuit, one changes the programme memory chips.
- the random access memory is used as data workspace by the processor when executing the programmes from the programme memory. It is non-volatile so that when power is removed the contents of the RAM do not corrupt.
- the video memory is a complete dot image of the screen. To alter the displayed image, the processor, under control of the programme memory, writes to the video memory to alter information displayed. For convenience the video memory can also be read.
- CMOS RAM 42 with battery back-up is employed for the data memory.
- An option is available whereby, when the programme memory is placed upon a separate memory module PCB, the CMOS RAM is also placed there together with its battery back-up and circuitry for protecting the CMOS RAM from data corruption during power supply interruption and/or malicious or otherwise interference.
- This facility permits non-volatile data on machine performance, to be retained, even when the control unit is replaced, should it become faulty, because the programme module will remain with the equipment even if the rest of the controller has to be replaced.
- the sound generator 40 operates using a fairly conventional method of sound generation utilising the General Instruments Chip AY-3-8912.
- a multiplexed input scheme 51 is employed, with 3 bytes, each of 8 bits, being enabled by switch common 1, 2 or 3. Steering diodes are used to separate data from one byte to the next.
- the switch commoned strobe and the 8 bits of input all connect to the input/output lines available on the sound generator chip40.
- the multiplexed input bytes can be gated onto the processor bus for inputs using a tri-state buffer, though in this particular application they connect via the tri-state buffers contained within the sound effects generating chip 40.
- Addressable output latches 44, 46, 48, 50 are utilised, which connect directly to the Processor Address and Data Bus, providing 32 lines of output.
- Each output may be similar, consisting of a Darlington transistor together with at least one, and preferably a pair, of safety catch diodes or one or more of the outputs may be changed to drive a triac.
- a switching regulated power supply 52 (fig.2) is employed to generate logic rail at 5 volts, l.5amps nominal from a 24 volts AC input.
- the fullwave rectified 24 volts rail, and the +24 volts DC rail, are also used to provide a feed to the loads which are connected to the outputs as described above.
- a quad 2-input Schmidt trigger CMOS package 53 is used to generate a power failure detect signal and a reset signal.
- This CMOS package is powered permanently from the battery used for the non-volatile RAM.
- the input is fed from a potential divider circuit, which ensures that at the worst case power fail detect is active 10 milliseconds before reset is active, which is active 10 milliseconds before the 5 volt droops.
- On power up an RC timing circuit ensures that reset remains active for at least 200 milliseconds after the 5 volt rail is established.
- this reset/power fail detect circuit would also appear on that module, as the reset output is used to protect the RAM Chip Selects during power down conditions.
- the addresses on the address bus 14, are given the prefix A and the data lines are given the prefix D.
- the signals from the clock pulse generator and controller 23 are referenced and connected as indicated to the Processor and other circuits. Where not otherwise indicated connecting lines at the same level are used to indicate connection of the same signals to similar circuits.
- the addresses A o to A 8 are connected to all of the sixteen memories.
- this period represents in time the period of displaying four dots horizontally on the screen.
- This 400 nanoseconds is split into two halves. The first half of 250 nanoseconds is not used by the video circuit and is available for the processor to access the video memory for read or write should the processor require to do so. Circuitry is embodied which provides for transparent access during this period. Hence the processor can access the video memory 50 per cent of the time, and the maximum that the processor has to wait is 200 nanoseconds. The second half of the cycle of 200 nanoseconds is always used by the video circuit to do a video access to the video memory.
- a memory read is performed during this period and the 16 bits read are clocked into the shift registers at the end of this period.
- the shift registers are clocked four times, i.e., every 100 nanoseconds.
- the four dots loaded in parallel at the end of the previoust 400 nanosecond cycle are made available to the video circuit sequentially every 100 nanoseconds throughout the following 400 nanosecond clock period.
- a line of 512 dots is displayed in 51.2 ⁇ s, every 64 ⁇ seconds giving a display time of approximately 30 milliseconds per picture of 512 lines.
- the video controller generates clocks for additional lines to ensure that the total number of lines is that of a standard line system, e.g., 625 lines.
- the 625 lines are repeated every 40 milliseconds.
- the video controller 16 interlaces alternate lines every other frame.
- the video controller may also be initialised for other line systems, e.g. 525 lines 60 Hz.
- the access time of 200 nanoseconds is acceptable for most fast memories, latches etc., and therefor the circuit allows the display from a digital memory of information on a screen allowing individual dot discrimination.
- the microprocessor can change the information in for example the colour look up RAMS via the data lines DO to D11 on the information in the Video RAMS 20.
- the video circuit utilieses the colour look-up RAMS continuously throughout the displayed area of the screen, it is necessary to synchronise updating of the colour look-up RAMS to the frame fly-back period if the display is not to be affected momentarily during one or more dots.
- the colour look up RAMS give the colour information relating to each dot at a rate of four times the clock pulse i.e., every 100 nanoseconds.
- the D to A converters must be able to cope with this conversion rate.
- a programmable logic array 60 is inserted into the circuitry and the inputs of this array are connected for example to one or more of the outputs from the microprocessor.
- the outputs of the array are connected to other points in the rest of the circuitry.
- the programmable logic array may be made from a .programmable array logic it will not be possible to duplicate this without a great deal of work because if it is of the "burn in" type it will not be possible to easily determine the pattern used.
- An alternative could be a shift register with complex feedback paths which could be burned out to give an incripted output after say a delay of three or four clock pulse periods.
- the information in the Programme PROM could be modified for-example by inversion of every other bit and an output device which re-inverted every other bit could be used to correct the programme sequence prior to its use in the machine.
- the two inputs to the multiplexer come respectively from the multiplexer 18 and the processor address bus, and generate an address for the colour map RAM.
- the colour map RAM data inputs connect to the processor data bus with the data outputs connecting through the D-type latch to the additional high order address lines of the colour look-up RAM 28, 30, 32.
- "Two" raised to the power of the colour map RAM width defines the number of different colour look up table available, each table having the standard number of sixteen entries.
- the circuit functions as follows: each area of the screen is effectively described by the address emanating from block 18 when a video read is in process. This is fed via the multiplexer to the colour map RAM, which determines which set of colours is to be used for this area of the screen. This is effected by the output of the colour map RAM generating high order address lines to the colour look-up RAMS to page from one set of 16 look-up colours to another set of 16 look-up colours.
- the D -type latch ensures that transition from one to another occurs synchronously at the end of a four dot clock period.
- the processor has the ability to write to the colour map RAM using the address bus and data bus with the multiplexer correctly selected, and can thereby define which colour look-up tables are used on which section of the screen.
- One possible arrangement would be for the screen to be split up into blocks of 16 dots x 16 dots, and a location allocated in the colour map RAM for each particular block. In this way a total of 64 x 64 pages of colour look-up would be possible.
- Another arrangement could have a 64K by 1 bit RAM in parallel with video memory to give just two banks of tables with a total possible number of colours 32.
- Each 4 adjacent horizontal dots would then select one bank or the other as determined by the contents of the corresponding bit in the 64K colour map RAM. In some applications it may not be a requirement to have the colour map RAM at all in which case the output from multiplexer 26 would drive the red, green and blue lines in a binary manner.
- the display then awaits the operation of switches on the machine or if none are operated it proceeds to the next display and writes further video data into the video memory 20 from the main memory 42 as specified by the programme.
- the programme can take any suitable form giving a desired sequence of displays.
- video data When video data is transferred from memory 42 to video memory 20 it is transferred to specified positions in the memory 20 as specified by the programme and by information stored in the microprocessor for example as a result of operation of switches on the machine.
- This enables the display of four pixels per word (16 bits) or two pixels per byte (8 bits) of data on the screen and hence gives a better picture definition than previously obtainable.
- This system enables a number of effects to be obtained in a simple manner.
- a forshortening effect can be produced to give characters a fraction of the size of the centrally diplayed character to give the effect of a circular reel.
- a character is stored in memory 42 to require ten lines (0 - 9) of display then normally it will be stored in memory 20 as ten lines (0 - 9).
- every other line can be omitted when the character is transferred to memory 20.
- lines 0, 2, 4, 6, and 8 will be stored in five positions in memory 20 and thus the character will appear on the screen as half size in height.
- the information on colour in the video memory 20 is held as a number between one and sixteen. This number is converted by the colour look up memories and D to A converters into the displayed colour. This can be used to advantage. For example if a symbol is displayed on the screen in a variety of colours then on depression of a switch or after a time out period the colours can all be changed by the microprocessor transforming the colour numbers for that symbol in the video memory 20. As a simple case it could add one (1) to all colour numbers. Thus where a symbol was red blue and green (colour numbers 2, 3 and 4) it could become blue green and yellow (numbers 3, 4 and 5) by adding one to all the colour numbers. If done on a repetitive sequential time-out basis then the symbol will flash from one colour to another. In thç same manner silhouettes can be achieved.
- FIG. 5 A further method of altering the characters displayed is shown in Figure 5.
- a symbol "A" is displayed in two colours 1 and 2, then by initialising a short programme stored in memory 42 to change the colour map contents as contained in the memories 28, 30, 32 the colour of the symbol stored in video memory 20 can be changed as displayed even though its colour numbers as stored in memory 20 are not changed.
- the delays are built into the programme because otherwise the change of colour would occur too rapidly for the human eye to see.
- This technique can be used to provide flashing symbols and for example time effect colour changing pictures such as sunsets etc.
- a further feature of the system is in the display of pictures with large areas of symbols which must appear to move smoothly such as for example the simulation of reels moving on a fruit machine.
- To provide an acceptable picture it is proposed to update only for example every second, third or fourth line for each "frame" in a cyclic manner using a software interlace technique provided by a programme stored in the memory 42.
- a software interlace technique provided by a programme stored in the memory 42.
- a further feature of the system is that by writing video data directly into the colour map random access memory a picture can be displayed which can switch from between four separate black and white pictures without rewriting the video data in the memory 20 which is responsible for the actual figure or number displayed.
- a "flashing" announcement board type of display can be provided to switch between messages without updating memory 20 but merely by changing the colour look-up map.
- a further feature is the possibility of displaying a symbol on an already existing background without surrounding it with a different colour.
- the letter “A” is shown in a rectangular block as two colours 1 and 2. If colour 1 is stored as a zero colour say colour number "0" which has no colour then when the symbol block is displayed only the "A" will be displayed, the rest of the block being the colour of the background of the screen.
- each byte stored in the video memory 20 can be used to store only one pixel.
- an individual pixel can be addressed as opposed to the previously described arrangement in which with the storage of two pixels per byte it is only possible to address two pixels together and therefore four pixels per word using the 16 bit microprocessor.
- By not packing each byte it is easier therefore by storing for example only one pixel per byte to change one pixel on the display as a read of the packed pixels prior to modification is not required.
- a modified decoding circuit is required to ensure that the correct four address bits are used for addressing the single pixel within a byte or word.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8200883 | 1982-01-13 | ||
GB8200883 | 1982-01-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0085480A2 true EP0085480A2 (fr) | 1983-08-10 |
EP0085480A3 EP0085480A3 (fr) | 1986-01-08 |
Family
ID=10527594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP83300104A Withdrawn EP0085480A3 (fr) | 1982-01-13 | 1983-01-10 | Systèmes d'affichage vidéo |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0085480A3 (fr) |
AU (1) | AU1030683A (fr) |
GB (1) | GB2116004A (fr) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0148564A2 (fr) * | 1983-11-29 | 1985-07-17 | Tandy Corporation | Système de représentation graphique vidéo à résolution élevée |
EP0161319A1 (fr) * | 1983-10-25 | 1985-11-21 | Fanuc Ltd. | Appareil de commande d'ecriture et de lecture en relation a une memoire graphique |
EP0163863A2 (fr) * | 1984-04-13 | 1985-12-11 | Ascii Corporation | Système de commande d'affichage vidéo pour la visualisation d'images mobiles |
FR2605131A1 (fr) * | 1987-09-21 | 1988-04-15 | Ibm | Systeme d'affichage numerique a balayage de trame |
EP0264603A2 (fr) * | 1986-10-14 | 1988-04-27 | International Business Machines Corporation | Système numérique d'affichage à balayage à trame |
US4811007A (en) * | 1983-11-29 | 1989-03-07 | Tandy Corporation | High resolution video graphics system |
EP0383367A2 (fr) * | 1983-12-26 | 1990-08-22 | Hitachi, Ltd. | Appareil de traitement de motif graphique |
EP1271280A2 (fr) * | 2001-06-27 | 2003-01-02 | Microsoft Corporation | Carte vidéo sécurisée dans un dispositif informatique avec système de gestion des droits numériques (DRM) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6195629A (ja) * | 1984-10-16 | 1986-05-14 | Sony Corp | テレビジヨン受像機 |
US7370212B2 (en) | 2003-02-25 | 2008-05-06 | Microsoft Corporation | Issuing a publisher use license off-line in a digital rights management (DRM) system |
US8725646B2 (en) | 2005-04-15 | 2014-05-13 | Microsoft Corporation | Output protection levels |
US20060265758A1 (en) | 2005-05-20 | 2006-11-23 | Microsoft Corporation | Extensible media rights |
-
1983
- 1983-01-10 GB GB08300502A patent/GB2116004A/en not_active Withdrawn
- 1983-01-10 EP EP83300104A patent/EP0085480A3/fr not_active Withdrawn
- 1983-01-12 AU AU10306/83A patent/AU1030683A/en not_active Abandoned
Non-Patent Citations (2)
Title |
---|
ELECTRONIQUE INDUSTRIELLE, no. 21, October 1981, pages 33-36, Paris, FR; Ph. LAMBINET: "Réalisation d'un terminal graphique autour du processeur intégré EF 9365" * |
WESCON CONFERENCE RECORD, vol. 25, September 1981, pages 1-10(31/5), El Sequndo, CA, US; J.L. WISE et al.: "Color graphics with an advanced LSI controller" * |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0161319A1 (fr) * | 1983-10-25 | 1985-11-21 | Fanuc Ltd. | Appareil de commande d'ecriture et de lecture en relation a une memoire graphique |
EP0161319A4 (fr) * | 1983-10-25 | 1986-04-02 | Fanuc Ltd | Appareil de commande d'ecriture et de lecture en relation a une memoire graphique. |
US4811007A (en) * | 1983-11-29 | 1989-03-07 | Tandy Corporation | High resolution video graphics system |
EP0148564A2 (fr) * | 1983-11-29 | 1985-07-17 | Tandy Corporation | Système de représentation graphique vidéo à résolution élevée |
EP0148564A3 (en) * | 1983-11-29 | 1988-02-10 | Tandy Corporation | High resolution video graphics system |
US5332995A (en) * | 1983-12-26 | 1994-07-26 | Hitachi, Ltd. | Graphic pattern processing apparatus |
EP0383367A3 (fr) * | 1983-12-26 | 1993-05-19 | Hitachi, Ltd. | Appareil de traitement de motif graphique |
US6492992B2 (en) | 1983-12-26 | 2002-12-10 | Hitachi, Ltd. | Graphic pattern processing apparatus |
US5300947A (en) * | 1983-12-26 | 1994-04-05 | Hitachi, Ltd. | Graphic pattern processing apparatus |
EP0383367A2 (fr) * | 1983-12-26 | 1990-08-22 | Hitachi, Ltd. | Appareil de traitement de motif graphique |
EP0163863A3 (en) * | 1984-04-13 | 1989-02-22 | Ascii Corporation | Video display control system for animation pattern image |
EP0163863A2 (fr) * | 1984-04-13 | 1985-12-11 | Ascii Corporation | Système de commande d'affichage vidéo pour la visualisation d'images mobiles |
US4864289A (en) * | 1984-04-13 | 1989-09-05 | Ascii Corporation | Video display control system for animation pattern image |
BE1001063A3 (fr) * | 1986-10-14 | 1989-06-27 | Ibm | Systeme d'affichage numerique a balayage de trame. |
EP0264603A3 (en) * | 1986-10-14 | 1989-03-22 | International Business Machines Corporation | Raster scan digital display system |
EP0264603A2 (fr) * | 1986-10-14 | 1988-04-27 | International Business Machines Corporation | Système numérique d'affichage à balayage à trame |
FR2605131A1 (fr) * | 1987-09-21 | 1988-04-15 | Ibm | Systeme d'affichage numerique a balayage de trame |
EP1271280A2 (fr) * | 2001-06-27 | 2003-01-02 | Microsoft Corporation | Carte vidéo sécurisée dans un dispositif informatique avec système de gestion des droits numériques (DRM) |
EP1271280A3 (fr) * | 2001-06-27 | 2005-09-28 | Microsoft Corporation | Carte vidéo sécurisée dans un dispositif informatique avec système de gestion des droits numériques (DRM) |
CN1294499C (zh) * | 2001-06-27 | 2007-01-10 | 微软公司 | 具有数字权利管理***的计算设备中的安全视频卡 |
Also Published As
Publication number | Publication date |
---|---|
GB8300502D0 (en) | 1983-02-09 |
AU1030683A (en) | 1983-07-21 |
GB2116004A (en) | 1983-09-14 |
EP0085480A3 (fr) | 1986-01-08 |
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