DE69828131D1 - Nichtflüchtige Halbleiterspeicheranordnung und Schreibverfahren dafür - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung und Schreibverfahren dafür

Info

Publication number
DE69828131D1
DE69828131D1 DE69828131T DE69828131T DE69828131D1 DE 69828131 D1 DE69828131 D1 DE 69828131D1 DE 69828131 T DE69828131 T DE 69828131T DE 69828131 T DE69828131 T DE 69828131T DE 69828131 D1 DE69828131 D1 DE 69828131D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
method therefor
volatile semiconductor
writing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69828131T
Other languages
English (en)
Other versions
DE69828131T2 (de
Inventor
Yoshiji Ohta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69828131D1 publication Critical patent/DE69828131D1/de
Application granted granted Critical
Publication of DE69828131T2 publication Critical patent/DE69828131T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5624—Concurrent multilevel programming and programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5631—Concurrent multilevel reading of more than one cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE69828131T 1997-10-07 1998-10-07 Nicht-flüchtige Halbleiterspeicheranordnung und Schreibverfahren dafür Expired - Fee Related DE69828131T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP27427097 1997-10-07
JP27427097A JP3572179B2 (ja) 1997-10-07 1997-10-07 不揮発性半導体記憶装置およびその書き込み方法

Publications (2)

Publication Number Publication Date
DE69828131D1 true DE69828131D1 (de) 2005-01-20
DE69828131T2 DE69828131T2 (de) 2005-11-03

Family

ID=17539328

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69828131T Expired - Fee Related DE69828131T2 (de) 1997-10-07 1998-10-07 Nicht-flüchtige Halbleiterspeicheranordnung und Schreibverfahren dafür

Country Status (6)

Country Link
US (1) US5995412A (de)
EP (1) EP0908894B1 (de)
JP (1) JP3572179B2 (de)
KR (1) KR100340922B1 (de)
DE (1) DE69828131T2 (de)
TW (1) TW403907B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4154771B2 (ja) * 1998-11-10 2008-09-24 ソニー株式会社 不揮発性半導体記憶装置およびそのデータ書き込み方法
JP3905990B2 (ja) 1998-12-25 2007-04-18 株式会社東芝 記憶装置とその記憶方法
JP4550855B2 (ja) * 2000-03-08 2010-09-22 株式会社東芝 不揮発性半導体記憶装置
KR100365524B1 (ko) * 2000-08-29 2002-12-18 엘지마이크론 주식회사 비관통선을 가지는 새도우 마스크 및 이의 제조방법
IT1320699B1 (it) * 2000-10-06 2003-12-10 St Microelectronics Srl Memoria non volatile multilivello a ingombro ridotto e a basso consumo.
JP3631463B2 (ja) * 2001-12-27 2005-03-23 株式会社東芝 不揮発性半導体記憶装置
JP4170604B2 (ja) * 2001-04-18 2008-10-22 株式会社東芝 不揮発性半導体メモリ
JP3940570B2 (ja) * 2001-07-06 2007-07-04 株式会社東芝 半導体記憶装置
US6456557B1 (en) * 2001-08-28 2002-09-24 Tower Semiconductor Ltd Voltage regulator for memory device
US6714457B1 (en) * 2001-09-19 2004-03-30 Aplus Flash Technology, Inc. Parallel channel programming scheme for MLC flash memory
KR100769799B1 (ko) * 2001-12-20 2007-10-23 주식회사 하이닉스반도체 플래쉬 메모리 장치
JP2003346485A (ja) * 2002-05-23 2003-12-05 Fujitsu Ltd 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の書き込み方法
US7042044B2 (en) * 2004-02-18 2006-05-09 Koucheng Wu Nor-type channel-program channel-erase contactless flash memory on SOI
US7609548B2 (en) 2006-09-29 2009-10-27 Hynix Semiconductor Inc. Method of programming a multi level cell
KR100908518B1 (ko) * 2006-09-29 2009-07-20 주식회사 하이닉스반도체 멀티 레벨 셀의 프로그램 방법
WO2008077238A1 (en) * 2006-12-22 2008-07-03 Sidense Corp. Dual function data register
JP2014225309A (ja) 2013-05-16 2014-12-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0945094A (ja) * 1995-07-31 1997-02-14 Nkk Corp 不揮発性半導体記憶装置
JPH0969295A (ja) * 1995-08-31 1997-03-11 Sanyo Electric Co Ltd 不揮発性多値メモリ装置

Also Published As

Publication number Publication date
KR19990036689A (ko) 1999-05-25
JP3572179B2 (ja) 2004-09-29
JPH11110985A (ja) 1999-04-23
EP0908894A3 (de) 1999-06-16
US5995412A (en) 1999-11-30
DE69828131T2 (de) 2005-11-03
KR100340922B1 (ko) 2002-10-25
EP0908894A2 (de) 1999-04-14
EP0908894B1 (de) 2004-12-15
TW403907B (en) 2000-09-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee