DE69809868D1 - Pufferschicht zum Verbessern der Schichtdickenkontrolle - Google Patents

Pufferschicht zum Verbessern der Schichtdickenkontrolle

Info

Publication number
DE69809868D1
DE69809868D1 DE69809868T DE69809868T DE69809868D1 DE 69809868 D1 DE69809868 D1 DE 69809868D1 DE 69809868 T DE69809868 T DE 69809868T DE 69809868 T DE69809868 T DE 69809868T DE 69809868 D1 DE69809868 D1 DE 69809868D1
Authority
DE
Germany
Prior art keywords
thickness control
improve
layer
buffer layer
layer thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69809868T
Other languages
English (en)
Other versions
DE69809868T2 (de
Inventor
Ulrike Gruening
Jochen Beintner
Carl Radens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Application granted granted Critical
Publication of DE69809868D1 publication Critical patent/DE69809868D1/de
Publication of DE69809868T2 publication Critical patent/DE69809868T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)
DE69809868T 1997-09-26 1998-09-25 Pufferschicht zum Verbessern der Schichtdickenkontrolle Expired - Fee Related DE69809868T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/938,196 US6013937A (en) 1997-09-26 1997-09-26 Buffer layer for improving control of layer thickness

Publications (2)

Publication Number Publication Date
DE69809868D1 true DE69809868D1 (de) 2003-01-16
DE69809868T2 DE69809868T2 (de) 2003-10-09

Family

ID=25471075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69809868T Expired - Fee Related DE69809868T2 (de) 1997-09-26 1998-09-25 Pufferschicht zum Verbessern der Schichtdickenkontrolle

Country Status (7)

Country Link
US (1) US6013937A (de)
EP (1) EP0908938B1 (de)
JP (1) JPH11176930A (de)
KR (1) KR100509283B1 (de)
CN (1) CN1132240C (de)
DE (1) DE69809868T2 (de)
TW (1) TW393727B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD291059S (en) * 1984-04-12 1987-07-28 Dale Mickelson Caster assembly
US6013937A (en) * 1997-09-26 2000-01-11 Siemens Aktiengesellshaft Buffer layer for improving control of layer thickness
JPH11186514A (ja) * 1997-12-22 1999-07-09 Toshiba Corp 半導体記憶装置及びその製造方法
JP2000058802A (ja) 1998-01-13 2000-02-25 Stmicroelectronics Srl Ｓｏｉウェハの製造方法
US6190955B1 (en) * 1998-01-27 2001-02-20 International Business Machines Corporation Fabrication of trench capacitors using disposable hard mask
JP2000124305A (ja) * 1998-10-15 2000-04-28 Mitsubishi Electric Corp 半導体装置
GB9915589D0 (en) * 1999-07-02 1999-09-01 Smithkline Beecham Plc Novel compounds
EP1079426A1 (de) * 1999-08-16 2001-02-28 Applied Materials, Inc. Integrationsverfahren unter Verwendung einer selbstplanarisierten dielekrischen Schicht für flache Isolationsgräben (STI)
US6875558B1 (en) 1999-08-16 2005-04-05 Applied Materials, Inc. Integration scheme using self-planarized dielectric layer for shallow trench isolation (STI)
US6563144B2 (en) 1999-09-01 2003-05-13 The Regents Of The University Of California Process for growing epitaxial gallium nitride and composite wafers
FR2810792B1 (fr) * 2000-06-22 2003-07-04 Commissariat Energie Atomique Transistor mos vertical a grille enterree et procede de fabrication de celui-ci
US6368970B1 (en) 2000-08-24 2002-04-09 Infineon Technologies Ag Semiconductor configuration and corresponding production process
ATE501161T1 (de) * 2000-12-28 2011-03-15 Wyeth Llc Rekombinantes schutzprotein aus streptococcus pneumoniae
WO2004042783A2 (en) * 2002-05-17 2004-05-21 The Regents Of The University Of California Hafnium nitride buffer layers for growth of gan on silicon
US7238588B2 (en) * 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US7422961B2 (en) * 2003-03-14 2008-09-09 Advanced Micro Devices, Inc. Method of forming isolation regions for integrated circuits
US6673696B1 (en) * 2003-01-14 2004-01-06 Advanced Micro Devices, Inc. Post trench fill oxidation process for strained silicon processes
US6962857B1 (en) 2003-02-05 2005-11-08 Advanced Micro Devices, Inc. Shallow trench isolation process using oxide deposition and anneal
US7648886B2 (en) * 2003-01-14 2010-01-19 Globalfoundries Inc. Shallow trench isolation process
DE10312202B4 (de) * 2003-03-19 2005-06-02 Infineon Technologies Ag Verfahren zum Herstellen einer Ätzmaske auf einer Mikrostruktur, insbesondere einer Halbleiterstruktur mit Grabenkondensatoren, und entsprechende Verwendung der Ätzmaske
US6921709B1 (en) 2003-07-15 2005-07-26 Advanced Micro Devices, Inc. Front side seal to prevent germanium outgassing
US7462549B2 (en) * 2004-01-12 2008-12-09 Advanced Micro Devices, Inc. Shallow trench isolation process and structure with minimized strained silicon consumption
KR100616673B1 (ko) 2005-02-14 2006-08-28 삼성전기주식회사 절연코팅층을 갖는 반도성 칩 소자 및 그 제조방법
TWI280610B (en) * 2005-06-01 2007-05-01 Mosel Vitelic Inc Hard mask structure for deep trench super-junction device
KR100851916B1 (ko) * 2007-03-31 2008-08-12 주식회사 하이닉스반도체 비휘발성 메모리 소자의 제조방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
KR0140979B1 (ko) * 1989-10-20 1998-07-15 고스기 노부미쓰 반도체 집적회로 장치의 제조방법
WO1996002070A2 (en) * 1994-07-12 1996-01-25 National Semiconductor Corporation Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit
US5597756A (en) * 1995-06-21 1997-01-28 Micron Technology, Inc. Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack
US5643823A (en) * 1995-09-21 1997-07-01 Siemens Aktiengesellschaft Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures
US5656535A (en) * 1996-03-04 1997-08-12 Siemens Aktiengesellschaft Storage node process for deep trench-based DRAM
JP2000508474A (ja) * 1996-04-10 2000-07-04 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 改善された平坦化方法を伴う半導体トレンチアイソレーション
US5834358A (en) * 1996-11-12 1998-11-10 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US5776808A (en) * 1996-12-26 1998-07-07 Siemens Aktiengesellschaft Pad stack with a poly SI etch stop for TEOS mask removal with RIE
US5786262A (en) * 1997-04-09 1998-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-planarized gapfilling for shallow trench isolation
US6013937A (en) * 1997-09-26 2000-01-11 Siemens Aktiengesellshaft Buffer layer for improving control of layer thickness

Also Published As

Publication number Publication date
TW393727B (en) 2000-06-11
CN1132240C (zh) 2003-12-24
DE69809868T2 (de) 2003-10-09
JPH11176930A (ja) 1999-07-02
KR100509283B1 (ko) 2005-10-25
EP0908938A2 (de) 1999-04-14
EP0908938A3 (de) 1999-12-15
US6013937A (en) 2000-01-11
KR19990029365A (ko) 1999-04-26
EP0908938B1 (de) 2002-12-04
CN1218991A (zh) 1999-06-09

Similar Documents

Publication Publication Date Title
DE69809868D1 (de) Pufferschicht zum Verbessern der Schichtdickenkontrolle
DE19681316T1 (de) System zum Erweitern der Ziehfunktion
ID23867A (id) Lapisan penyekat-panas
FI961543A0 (fi) Kerrosmateriaali
DE69801255T2 (de) Gerät zum Festhalten
ID24258A (id) Komposisi untuk menghasilkan suatu lapisan tahan-abrasi pada substrat
DE69504811D1 (de) Gegenstand zum uebertragen von graphik
DE69630976D1 (de) Zusammensetzung zum kauen
DE69811489D1 (de) Kohlenstoff-siliciumcarbid-verbundwerkstoff
ID22050A (id) Bahan lapisan
DE897420T1 (de) Zusammensetzung zum entschichten von photolack
DE69822707D1 (de) Tintenstrahlaufzeichnungsschicht
DE69424529T2 (de) Zusammensetzung zum Läppen
DE69908679D1 (de) Verfahren zum Weitern
DE69509547T2 (de) Einschichtiger klebstoff zum verkleben von gegossenen polyurethanen an metall
NO954922D0 (no) AHUK - Isolerende laget
DE59705626D1 (de) Bildschirm mit haftungsvermittelnder Silikatschicht
DE69509376D1 (de) Mörtelunterschicht
DE69710728D1 (de) Zusammensetzungen zum entfernen von kalkstein
DE50008574D1 (de) Gelenk zum verbinden von drei hebeln
FR2773041B1 (fr) Tunnel acoustique
IT1287626B1 (it) Forno monostrato per piastrelle
KR950023418U (ko) 결속구조가 구비된 수로용 법면블럭
DE59913748D1 (de) Saugfähige Verbundschicht
ID20774A (id) Komposisi lapisan kertas

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE

Owner name: IBM INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,

8339 Ceased/non-payment of the annual fee