DE69737179D1 - Datenprozessorsynchronisation mit externem Bus - Google Patents

Datenprozessorsynchronisation mit externem Bus

Info

Publication number
DE69737179D1
DE69737179D1 DE69737179T DE69737179T DE69737179D1 DE 69737179 D1 DE69737179 D1 DE 69737179D1 DE 69737179 T DE69737179 T DE 69737179T DE 69737179 T DE69737179 T DE 69737179T DE 69737179 D1 DE69737179 D1 DE 69737179D1
Authority
DE
Germany
Prior art keywords
data processor
external bus
processor synchronization
synchronization
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69737179T
Other languages
English (en)
Other versions
DE69737179T2 (de
Inventor
Miki Urano
Keizo Sumida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69737179D1 publication Critical patent/DE69737179D1/de
Application granted granted Critical
Publication of DE69737179T2 publication Critical patent/DE69737179T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
DE69737179T 1996-10-29 1997-10-23 Datenprozessorsynchronisation mit externem Bus Expired - Lifetime DE69737179T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28635696 1996-10-29
JP28635696 1996-10-29

Publications (2)

Publication Number Publication Date
DE69737179D1 true DE69737179D1 (de) 2007-02-15
DE69737179T2 DE69737179T2 (de) 2007-04-19

Family

ID=17703326

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69737179T Expired - Lifetime DE69737179T2 (de) 1996-10-29 1997-10-23 Datenprozessorsynchronisation mit externem Bus

Country Status (3)

Country Link
US (1) US5940599A (de)
EP (1) EP0840237B1 (de)
DE (1) DE69737179T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052754A (en) * 1998-05-14 2000-04-18 Vlsi Technology, Inc. Centrally controlled interface scheme for promoting design reusable circuit blocks
US6651199B1 (en) * 2000-06-22 2003-11-18 Xilinx, Inc. In-system programmable flash memory device with trigger circuit for generating limited duration program instruction
FR2839827B1 (fr) * 2002-05-14 2005-07-15 St Microelectronics Sa Circuit de detection de depart, circuit de detection d'arret, et circuit de detection de donnees transmises selon le protocole iic
FR2870368B1 (fr) * 2004-01-27 2006-12-15 Atmel Corp Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre
US20060259807A1 (en) * 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Method and apparatus for clock synchronization between a processor and external devices
WO2006121437A1 (en) * 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Method and apparatus for clock synchronization between a processor and external devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0285951A (ja) * 1988-06-08 1990-03-27 Nec Corp 入出力バス・サイクル制御方式
US5291070A (en) * 1991-01-28 1994-03-01 Advanced Micro Devices, Inc. Microprocessor synchronous timing system
US5272729A (en) * 1991-09-20 1993-12-21 International Business Machines Corporation Clock signal latency elimination network
JP2770656B2 (ja) * 1992-05-11 1998-07-02 ヤマハ株式会社 集積回路装置
US5811998A (en) * 1993-01-28 1998-09-22 Digital Equipment Corporation State machine phase lock loop
US5422914A (en) * 1993-09-07 1995-06-06 Motorola, Inc. System and method for synchronizing data communications between two devices operating at different clock frequencies
US5485602A (en) * 1993-12-27 1996-01-16 Motorola, Inc. Integrated circuit having a control signal for identifying coinciding active edges of two clock signals

Also Published As

Publication number Publication date
US5940599A (en) 1999-08-17
DE69737179T2 (de) 2007-04-19
EP0840237B1 (de) 2007-01-03
EP0840237A1 (de) 1998-05-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP