FR2870368B1 - Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre - Google Patents
Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integreInfo
- Publication number
- FR2870368B1 FR2870368B1 FR0400740A FR0400740A FR2870368B1 FR 2870368 B1 FR2870368 B1 FR 2870368B1 FR 0400740 A FR0400740 A FR 0400740A FR 0400740 A FR0400740 A FR 0400740A FR 2870368 B1 FR2870368 B1 FR 2870368B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- clock frequencies
- different clock
- driving multiple
- multiple peripherals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0400740A FR2870368B1 (fr) | 2004-01-27 | 2004-01-27 | Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre |
US11/036,471 US7162003B2 (en) | 2004-01-27 | 2005-01-13 | Method and apparatus for driving multiple peripherals with different clock frequencies in an integrated circuit |
EP05706040A EP1709737A1 (fr) | 2004-01-27 | 2005-01-20 | Methode et appareil de commande de peripheriques multiples a differentes frequences d'horloge dans un circuit integre |
PCT/US2005/002122 WO2005074135A1 (fr) | 2004-01-27 | 2005-01-20 | Methode et appareil de commande de peripheriques multiples a differentes frequences d'horloge dans un circuit integre |
CNB2005800017389A CN100547924C (zh) | 2004-01-27 | 2005-01-20 | 在集成电路中以不同时钟频率驱动多个***设备的方法和装置 |
TW094102467A TW200604823A (en) | 2004-01-27 | 2005-01-27 | Method and apparatus for driving multiple peripherals with different clock frequencies in an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0400740A FR2870368B1 (fr) | 2004-01-27 | 2004-01-27 | Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2870368A1 FR2870368A1 (fr) | 2005-11-18 |
FR2870368B1 true FR2870368B1 (fr) | 2006-12-15 |
Family
ID=34778519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0400740A Expired - Fee Related FR2870368B1 (fr) | 2004-01-27 | 2004-01-27 | Procede et dispositif pour piloter de multiples peripheriques avec des frequences d'horloge differentes dans un circuit integre |
Country Status (4)
Country | Link |
---|---|
US (1) | US7162003B2 (fr) |
CN (1) | CN100547924C (fr) |
FR (1) | FR2870368B1 (fr) |
TW (1) | TW200604823A (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7100061B2 (en) * | 2000-01-18 | 2006-08-29 | Transmeta Corporation | Adaptive power control |
US7539078B2 (en) * | 2006-08-22 | 2009-05-26 | Atmel Corporation | Circuits to delay a signal from a memory device |
US7433262B2 (en) * | 2006-08-22 | 2008-10-07 | Atmel Corporation | Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction |
US9397668B2 (en) * | 2014-12-18 | 2016-07-19 | Linear Technology Corporation | System and method for providing programmable synchronous output delay in a clock generation or distribution device |
US10503686B2 (en) * | 2015-12-09 | 2019-12-10 | Microchip Technology Incorporated | SPI interface with automatic slave select generation |
CN109901664B (zh) * | 2019-02-27 | 2020-03-27 | 苏州浪潮智能科技有限公司 | 提供时钟信号的方法、装置、***、设备及可读存储介质 |
CN112447218A (zh) | 2019-08-29 | 2021-03-05 | 台湾积体电路制造股份有限公司 | 存储器电路和方法 |
DE102019128331A1 (de) | 2019-08-29 | 2021-03-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gemeinsam genutzter decodiererschaltkreis und verfahren |
CN114499508A (zh) * | 2020-11-13 | 2022-05-13 | 瑞昱半导体股份有限公司 | 操作时钟产生装置与参考时钟栅控电路 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4030451A1 (de) * | 1990-09-26 | 1992-04-09 | Siemens Ag | Verfahren und vorrichtung zur direkten erzeugung von wartezyklen fuer elektronische einrichtungen, insbesondere fuer mikroprozessoren |
DE4030541C2 (de) | 1990-09-27 | 1997-10-02 | Dilthey Ulrich Prof Dr Ing | Brenner zur Beschichtung von Grundwerkstoffen mit pulverförmigen Zusatzwerkstoffen |
GB2252432B (en) | 1991-02-01 | 1994-09-28 | Intel Corp | Method and apparatus for operating a computer bus using selectable clock frequencies |
US5678065A (en) | 1994-09-19 | 1997-10-14 | Advanced Micro Devices, Inc. | Computer system employing an enable line for selectively adjusting a peripheral bus clock frequency |
US5586308A (en) | 1994-10-19 | 1996-12-17 | Advanced Micro Devices, Inc. | Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto |
EP0708406B1 (fr) | 1994-10-19 | 2001-09-12 | Advanced Micro Devices, Inc. | Systèmes processeurs intégrés pour dispositifs d'information portables |
BR9509870A (pt) * | 1994-12-08 | 1997-11-25 | Intel Corp | Método e aparelho para permitir a um processador acessar um componente externo através de um barramento privado ou um barramento compartílhado |
US5838995A (en) | 1995-12-18 | 1998-11-17 | International Business Machines Corporation | System and method for high frequency operation of I/O bus |
EP0840237B1 (fr) * | 1996-10-29 | 2007-01-03 | Matsushita Electric Industrial Co., Ltd. | Synchronisation de processeur avec bus externe |
JPH10334037A (ja) * | 1997-05-30 | 1998-12-18 | Sanyo Electric Co Ltd | 通信dma装置 |
JPH11184554A (ja) | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | クロック制御タイプ情報処理装置 |
FR2773625B1 (fr) | 1998-01-13 | 2003-01-03 | Sgs Thomson Microelectronics | Microcontroleur a vitesse de fonctionnement amelioree |
US6912637B1 (en) * | 1998-07-08 | 2005-06-28 | Broadcom Corporation | Apparatus and method for managing memory in a network switch |
US6564329B1 (en) | 1999-03-16 | 2003-05-13 | Linkup Systems Corporation | System and method for dynamic clock generation |
US6457137B1 (en) | 1999-05-28 | 2002-09-24 | 3Com Corporation | Method for configuring clock ratios in a microprocessor |
US6345328B1 (en) | 1999-06-09 | 2002-02-05 | Advanced Micro Devices, Inc. | Gear box for multiple clock domains |
US6510473B1 (en) | 1999-08-19 | 2003-01-21 | Micron Technology, Inc. | Apparatus and method for automatically selecting an appropriate signal from a plurality of signals, based on the configuration of a peripheral installed within a computing device |
US6393502B1 (en) * | 1999-08-31 | 2002-05-21 | Advanced Micro Devices, Inc. | System and method for initiating a serial data transfer between two clock domains |
US6643787B1 (en) * | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US6513126B1 (en) * | 2000-01-06 | 2003-01-28 | Lsi Logic Corporation | System for modeling a processor-encoder interface by counting number of fast clock cycles occuring in one slower clock cycle and triggering a domain module if fast clock reaches the corresponding number of cycles |
US6633994B1 (en) | 2000-02-22 | 2003-10-14 | International Business Machines Corporation | Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds |
US6747997B1 (en) * | 2000-06-13 | 2004-06-08 | Intel Corporation | Network channel receiver architecture |
JP2002041452A (ja) * | 2000-07-27 | 2002-02-08 | Hitachi Ltd | マイクロプロセッサ、半導体モジュール及びデータ処理システム |
US6802015B2 (en) * | 2000-12-29 | 2004-10-05 | Hewlett-Packard Development Company, L.P. | Method for accelerating the speed of a CPU using a system command having an operation not associated with changing the speed of the CPU |
US6789153B1 (en) * | 2001-02-20 | 2004-09-07 | Lsi Logic Corporation | Bridge for coupling digital signal processor to on-chip bus as slave |
US7089441B2 (en) * | 2001-02-27 | 2006-08-08 | Intel Corporation | Clock multiplier selection for a microprocessor with multiple system bus clocking frequencies |
JP3510618B2 (ja) | 2002-02-05 | 2004-03-29 | 沖電気工業株式会社 | バスブリッジ回路及びそのアクセス制御方法 |
-
2004
- 2004-01-27 FR FR0400740A patent/FR2870368B1/fr not_active Expired - Fee Related
-
2005
- 2005-01-13 US US11/036,471 patent/US7162003B2/en active Active
- 2005-01-20 CN CNB2005800017389A patent/CN100547924C/zh not_active Expired - Fee Related
- 2005-01-27 TW TW094102467A patent/TW200604823A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
CN1906851A (zh) | 2007-01-31 |
US7162003B2 (en) | 2007-01-09 |
TW200604823A (en) | 2006-02-01 |
CN100547924C (zh) | 2009-10-07 |
FR2870368A1 (fr) | 2005-11-18 |
US20050165996A1 (en) | 2005-07-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20120928 |