DE69622922T2 - Leiterplatte für Elektronikkomponenten mit hochdichten Anschlüssen und ihre Herstellung - Google Patents

Leiterplatte für Elektronikkomponenten mit hochdichten Anschlüssen und ihre Herstellung

Info

Publication number
DE69622922T2
DE69622922T2 DE69622922T DE69622922T DE69622922T2 DE 69622922 T2 DE69622922 T2 DE 69622922T2 DE 69622922 T DE69622922 T DE 69622922T DE 69622922 T DE69622922 T DE 69622922T DE 69622922 T2 DE69622922 T2 DE 69622922T2
Authority
DE
Germany
Prior art keywords
manufacture
circuit board
printed circuit
electronic components
density connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69622922T
Other languages
English (en)
Other versions
DE69622922D1 (de
Inventor
Tatsuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69622922D1 publication Critical patent/DE69622922D1/de
Publication of DE69622922T2 publication Critical patent/DE69622922T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Multi-Conductor Connections (AREA)
DE69622922T 1995-05-18 1996-05-17 Leiterplatte für Elektronikkomponenten mit hochdichten Anschlüssen und ihre Herstellung Expired - Fee Related DE69622922T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7119573A JP2833521B2 (ja) 1995-05-18 1995-05-18 配線基板

Publications (2)

Publication Number Publication Date
DE69622922D1 DE69622922D1 (de) 2002-09-19
DE69622922T2 true DE69622922T2 (de) 2003-04-24

Family

ID=14764700

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69622922T Expired - Fee Related DE69622922T2 (de) 1995-05-18 1996-05-17 Leiterplatte für Elektronikkomponenten mit hochdichten Anschlüssen und ihre Herstellung

Country Status (5)

Country Link
US (1) US5993946A (de)
EP (1) EP0743681B1 (de)
JP (1) JP2833521B2 (de)
CA (1) CA2176789C (de)
DE (1) DE69622922T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732732B2 (en) 1996-11-20 2010-06-08 Ibiden Co., Ltd. Laser machining apparatus, and apparatus and method for manufacturing a multilayered printed wiring board
DE19705198A1 (de) * 1997-02-12 1998-08-20 Polus Michael Substrat mit Leiterbahnvernetzung
JP2000156564A (ja) * 1998-11-20 2000-06-06 Nec Corp プリント配線板及びその製造方法
US6624500B2 (en) * 2000-11-30 2003-09-23 Kyocera Corporation Thin-film electronic component and motherboard
JP6375121B2 (ja) * 2014-02-27 2018-08-15 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN104952839B (zh) * 2014-03-28 2018-05-04 恒劲科技股份有限公司 封装装置及其制作方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3447038A (en) * 1966-08-01 1969-05-27 Us Navy Method and apparatus for interconnecting microelectronic circuit wafers
IL45626A (en) * 1973-10-09 1976-10-31 Hughes Aircraft Co Hybrid microcircuit fabrication aid
JPS54149646U (de) * 1978-04-11 1979-10-18
FR2556503B1 (fr) * 1983-12-08 1986-12-12 Eurofarad Substrat d'interconnexion en alumine pour composant electronique
JPS6156493A (ja) * 1984-08-28 1986-03-22 日本電気株式会社 多層回路基板の電源配線構造
US4731699A (en) * 1985-10-08 1988-03-15 Nec Corporation Mounting structure for a chip
US4733462A (en) * 1986-06-24 1988-03-29 Sony Corporation Apparatus for positioning circuit components at predetermined positions and method therefor
JPS6366993A (ja) * 1986-09-08 1988-03-25 日本電気株式会社 多層配線基板
GB2211667A (en) * 1986-12-29 1989-07-05 Motorola Inc Method for inspecting printed circuit boards for missing or misplaced components
US5034802A (en) * 1989-12-11 1991-07-23 Hewlett-Packard Company Mechanical simultaneous registration of multi-pin surface-mount components to sites on substrates
US5241134A (en) * 1990-09-17 1993-08-31 Yoo Clarence S Terminals of surface mount components
JPH04132295A (ja) * 1990-09-21 1992-05-06 Nec Corp 多層配線基板
JPH0567869A (ja) * 1991-09-05 1993-03-19 Matsushita Electric Ind Co Ltd 電装部品接合方法並びにモジユール及び多層基板
DE59208900D1 (de) * 1992-12-12 1997-10-16 Ibm Leiterplatten mit lokal erhöhter Verdrahtungsdichte und Herstellungsverfahren für solche Leiterplatten
JP3325351B2 (ja) * 1993-08-18 2002-09-17 株式会社東芝 半導体装置
JP2867313B2 (ja) * 1993-12-10 1999-03-08 日本特殊陶業株式会社 セラミック基板
JP2812358B2 (ja) * 1996-03-18 1998-10-22 日本電気株式会社 Ｌｓｉパッケージおよびｌｓｉパッケージ製造方法

Also Published As

Publication number Publication date
US5993946A (en) 1999-11-30
JP2833521B2 (ja) 1998-12-09
EP0743681B1 (de) 2002-08-14
EP0743681A2 (de) 1996-11-20
EP0743681A3 (de) 1997-08-20
CA2176789A1 (en) 1996-11-19
JPH08316643A (ja) 1996-11-29
DE69622922D1 (de) 2002-09-19
CA2176789C (en) 2000-11-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee