DE69534936D1 - Verfahren zum Verbinden integrierter Schaltungschips an Substraten - Google Patents

Verfahren zum Verbinden integrierter Schaltungschips an Substraten

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Publication number
DE69534936D1
DE69534936D1 DE69534936T DE69534936T DE69534936D1 DE 69534936 D1 DE69534936 D1 DE 69534936D1 DE 69534936 T DE69534936 T DE 69534936T DE 69534936 T DE69534936 T DE 69534936T DE 69534936 D1 DE69534936 D1 DE 69534936D1
Authority
DE
Germany
Prior art keywords
substrates
integrated circuit
circuit chips
connecting integrated
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69534936T
Other languages
English (en)
Other versions
DE69534936T2 (de
Inventor
Linden T Halstead
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
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Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69534936D1 publication Critical patent/DE69534936D1/de
Publication of DE69534936T2 publication Critical patent/DE69534936T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
DE69534936T 1994-05-31 1995-05-31 Verfahren zum Verbinden integrierter Schaltungschips an Substraten Expired - Fee Related DE69534936T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US250977 1994-05-31
US08/250,977 US5471017A (en) 1994-05-31 1994-05-31 No fixture method to cure die attach for bonding IC dies to substrates

Publications (2)

Publication Number Publication Date
DE69534936D1 true DE69534936D1 (de) 2006-05-24
DE69534936T2 DE69534936T2 (de) 2007-03-15

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DE69534936T Expired - Fee Related DE69534936T2 (de) 1994-05-31 1995-05-31 Verfahren zum Verbinden integrierter Schaltungschips an Substraten

Country Status (7)

Country Link
US (2) US5471017A (de)
EP (1) EP0687000B1 (de)
JP (1) JPH0845969A (de)
KR (1) KR100338018B1 (de)
DE (1) DE69534936T2 (de)
MY (1) MY112620A (de)
SG (1) SG28283A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232150B1 (en) 1998-12-03 2001-05-15 The Regents Of The University Of Michigan Process for making microstructures and microstructures made thereby
US6541872B1 (en) 1999-01-11 2003-04-01 Micron Technology, Inc. Multi-layered adhesive for attaching a semiconductor die to a substrate
US8188375B2 (en) * 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
US20080203566A1 (en) * 2007-02-27 2008-08-28 Chao-Yuan Su Stress buffer layer for packaging process

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4029628A (en) * 1974-05-22 1977-06-14 The United States Of America As Represented By The Secretary Of The Navy Bonding material for planar electronic device
CA1290676C (en) * 1987-03-30 1991-10-15 William Frank Graham Method for bonding integrated circuit chips
US5057900A (en) * 1988-10-17 1991-10-15 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5205036A (en) * 1988-10-17 1993-04-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with selective coating on lead frame
EP0384704A3 (de) * 1989-02-21 1991-05-08 General Electric Company Material für Würfelbefestigung und Verfahren zur Befestigung eines Würfels
US5225023A (en) * 1989-02-21 1993-07-06 General Electric Company High density interconnect thermoplastic die attach material and solvent die attach processing
US5204399A (en) * 1989-03-09 1993-04-20 National Starch And Chemical Investment Holding Corporation Thermoplastic film die attach adhesives
US5006575A (en) * 1989-10-20 1991-04-09 E. I. Du Pont De Nemours And Company Die attach adhesive composition
US5371328A (en) * 1993-08-20 1994-12-06 International Business Machines Corporation Component rework

Also Published As

Publication number Publication date
US5706577A (en) 1998-01-13
SG28283A1 (en) 1996-04-01
US5471017A (en) 1995-11-28
KR950034720A (ko) 1995-12-28
EP0687000B1 (de) 2006-04-19
EP0687000A1 (de) 1995-12-13
JPH0845969A (ja) 1996-02-16
DE69534936T2 (de) 2007-03-15
KR100338018B1 (ko) 2002-11-30
MY112620A (en) 2001-07-31

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