DE69526486D1 - Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung - Google Patents
Verfahren zum Herstellen einer Kontaktfläche in einer integrierten SchaltungInfo
- Publication number
- DE69526486D1 DE69526486D1 DE69526486T DE69526486T DE69526486D1 DE 69526486 D1 DE69526486 D1 DE 69526486D1 DE 69526486 T DE69526486 T DE 69526486T DE 69526486 T DE69526486 T DE 69526486T DE 69526486 D1 DE69526486 D1 DE 69526486D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- integrated circuit
- contact area
- contact
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/361,760 US5702979A (en) | 1994-05-31 | 1994-12-22 | Method of forming a landing pad structure in an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69526486D1 true DE69526486D1 (de) | 2002-05-29 |
DE69526486T2 DE69526486T2 (de) | 2002-10-10 |
Family
ID=23423349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69526486T Expired - Fee Related DE69526486T2 (de) | 1994-12-22 | 1995-11-30 | Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung |
Country Status (4)
Country | Link |
---|---|
US (3) | US5702979A (de) |
EP (1) | EP0718879B1 (de) |
JP (1) | JPH08236624A (de) |
DE (1) | DE69526486T2 (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5705427A (en) * | 1994-12-22 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
US6075266A (en) * | 1997-01-09 | 2000-06-13 | Kabushiki Kaisha Toshiba | Semiconductor device having MIS transistors and capacitor |
US5854127A (en) * | 1997-03-13 | 1998-12-29 | Micron Technology, Inc. | Method of forming a contact landing pad |
US6083803A (en) | 1998-02-27 | 2000-07-04 | Micron Technology, Inc. | Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances |
US6369423B2 (en) * | 1998-03-03 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device with a thin gate stack having a plurality of insulating layers |
US6121094A (en) * | 1998-07-21 | 2000-09-19 | Advanced Micro Devices, Inc. | Method of making a semiconductor device with a multi-level gate structure |
US6140688A (en) * | 1998-09-21 | 2000-10-31 | Advanced Micro Devices Inc. | Semiconductor device with self-aligned metal-containing gate |
JP2000114522A (ja) * | 1998-10-08 | 2000-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6288419B1 (en) * | 1999-07-09 | 2001-09-11 | Micron Technology, Inc. | Low resistance gate flash memory |
JP2001196413A (ja) * | 2000-01-12 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置、該半導体装置の製造方法、cmp装置、及びcmp方法 |
JP4979154B2 (ja) * | 2000-06-07 | 2012-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6376353B1 (en) * | 2000-07-03 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
JP2002208695A (ja) * | 2001-01-11 | 2002-07-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6706608B2 (en) * | 2001-02-28 | 2004-03-16 | Micron Technology, Inc. | Memory cell capacitors having an over/under configuration |
US6767778B2 (en) * | 2002-08-29 | 2004-07-27 | Micron Technology, Inc. | Low dose super deep source/drain implant |
US7462521B2 (en) * | 2004-11-29 | 2008-12-09 | Walker Andrew J | Dual-gate device and method |
DE102008043929A1 (de) * | 2008-11-20 | 2010-05-27 | Robert Bosch Gmbh | Elektronisches Bauelement |
KR102230194B1 (ko) | 2014-04-14 | 2021-03-19 | 삼성전자주식회사 | 반도체 소자 |
US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
US9397049B1 (en) | 2015-08-10 | 2016-07-19 | International Business Machines Corporation | Gate tie-down enablement with inner spacer |
US9768179B1 (en) * | 2016-11-18 | 2017-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connection structures for routing misaligned metal lines between TCAM cells and periphery circuits |
KR20220003870A (ko) | 2020-07-02 | 2022-01-11 | 삼성전자주식회사 | 반도체 메모리 장치 및 그 제조 방법 |
Family Cites Families (67)
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US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
JPS6116571A (ja) * | 1984-07-03 | 1986-01-24 | Ricoh Co Ltd | 半導体装置の製造方法 |
US4851895A (en) * | 1985-05-06 | 1989-07-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Metallization for integrated devices |
JPS62136856A (ja) * | 1985-12-11 | 1987-06-19 | Toshiba Corp | 半導体装置の製造方法 |
US5247199A (en) * | 1986-01-15 | 1993-09-21 | Harris Corporation | Process for forming twin well CMOS integrated circuits |
US4707457A (en) * | 1986-04-03 | 1987-11-17 | Advanced Micro Devices, Inc. | Method for making improved contact for integrated circuit structure |
JPS62272555A (ja) * | 1986-05-20 | 1987-11-26 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS63239973A (ja) * | 1986-10-08 | 1988-10-05 | テキサス インスツルメンツ インコーポレイテツド | 集積回路およびその製造方法 |
US4782380A (en) * | 1987-01-22 | 1988-11-01 | Advanced Micro Devices, Inc. | Multilayer interconnection for integrated circuit structure having two or more conductive metal layers |
US4795722A (en) * | 1987-02-05 | 1989-01-03 | Texas Instruments Incorporated | Method for planarization of a semiconductor device prior to metallization |
US4789885A (en) * | 1987-02-10 | 1988-12-06 | Texas Instruments Incorporated | Self-aligned silicide in a polysilicon self-aligned bipolar transistor |
US4884123A (en) * | 1987-02-19 | 1989-11-28 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
US4795718A (en) * | 1987-05-12 | 1989-01-03 | Harris Corporation | Self-aligned contact for MOS processing |
US4822449A (en) * | 1987-06-10 | 1989-04-18 | Massachusetts Institute Of Technology | Heat transfer control during crystal growth |
US5071783A (en) * | 1987-06-17 | 1991-12-10 | Fujitsu Limited | Method of producing a dynamic random access memory device |
JPH07114214B2 (ja) * | 1987-08-03 | 1995-12-06 | 三菱電機株式会社 | 半導体装置 |
US4822749A (en) * | 1987-08-27 | 1989-04-18 | North American Philips Corporation, Signetics Division | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten |
US5236867A (en) * | 1987-11-13 | 1993-08-17 | Matsushita Electronics Corporation | Manufacturing method of contact hole arrangement of a semiconductor device |
US5081516A (en) * | 1987-12-02 | 1992-01-14 | Advanced Micro Devices, Inc. | Self-aligned, planarized contacts for semiconductor devices |
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US4994410A (en) * | 1988-04-04 | 1991-02-19 | Motorola, Inc. | Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process |
JPH0797928B2 (ja) * | 1988-06-03 | 1995-10-25 | 井関農機株式会社 | 移動農作業機のローリング装置 |
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JPH0541378A (ja) * | 1991-03-15 | 1993-02-19 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH04307732A (ja) * | 1991-04-04 | 1992-10-29 | Kawasaki Steel Corp | 半導体装置及びその製造方法 |
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US5198683A (en) * | 1991-05-03 | 1993-03-30 | Motorola, Inc. | Integrated circuit memory device and structural layout thereof |
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US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
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US5298463A (en) * | 1991-08-30 | 1994-03-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer using a contact etch stop |
US5298792A (en) * | 1992-02-03 | 1994-03-29 | Micron Technology, Inc. | Integrated circuit device with bi-level contact landing pads |
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US5229326A (en) * | 1992-06-23 | 1993-07-20 | Micron Technology, Inc. | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
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JP2684978B2 (ja) * | 1993-11-25 | 1997-12-03 | 日本電気株式会社 | 半導体装置 |
US5420058A (en) * | 1993-12-01 | 1995-05-30 | At&T Corp. | Method of making field effect transistor with a sealed diffusion junction |
US5541137A (en) * | 1994-03-24 | 1996-07-30 | Micron Semiconductor Inc. | Method of forming improved contacts from polysilicon to silicon or other polysilicon layers |
US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
US5514622A (en) * | 1994-08-29 | 1996-05-07 | Cypress Semiconductor Corporation | Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole |
JP3016220B2 (ja) | 1994-12-27 | 2000-03-06 | 東急車輛製造株式会社 | 複合油圧シリンダ装置 |
DE19642141C1 (de) | 1996-10-12 | 1998-06-18 | Koenig & Bauer Albert Ag | Vorrichtung zum Lösen von Platten |
-
1994
- 1994-12-22 US US08/361,760 patent/US5702979A/en not_active Ceased
-
1995
- 1995-11-30 EP EP95308656A patent/EP0718879B1/de not_active Expired - Lifetime
- 1995-11-30 DE DE69526486T patent/DE69526486T2/de not_active Expired - Fee Related
- 1995-12-19 JP JP7330348A patent/JPH08236624A/ja active Pending
-
1996
- 1996-10-03 US US08/725,621 patent/US5894160A/en not_active Expired - Lifetime
-
1998
- 1998-08-17 US US09/134,727 patent/USRE36938E/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0718879B1 (de) | 2002-04-24 |
JPH08236624A (ja) | 1996-09-13 |
US5894160A (en) | 1999-04-13 |
USRE36938E (en) | 2000-10-31 |
US5702979A (en) | 1997-12-30 |
EP0718879A1 (de) | 1996-06-26 |
DE69526486T2 (de) | 2002-10-10 |
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