DE69527344D1 - Verfahren zur Herstellung einer Halbleiterverbindungsstruktur - Google Patents
Verfahren zur Herstellung einer HalbleiterverbindungsstrukturInfo
- Publication number
- DE69527344D1 DE69527344D1 DE69527344T DE69527344T DE69527344D1 DE 69527344 D1 DE69527344 D1 DE 69527344D1 DE 69527344 T DE69527344 T DE 69527344T DE 69527344 T DE69527344 T DE 69527344T DE 69527344 D1 DE69527344 D1 DE 69527344D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- interconnect structure
- semiconductor interconnect
- semiconductor
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US36621594A | 1994-12-29 | 1994-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69527344D1 true DE69527344D1 (de) | 2002-08-14 |
DE69527344T2 DE69527344T2 (de) | 2003-02-27 |
Family
ID=23442113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69527344T Expired - Lifetime DE69527344T2 (de) | 1994-12-29 | 1995-12-05 | Verfahren zur Herstellung einer Halbleiterverbindungsstruktur |
Country Status (4)
Country | Link |
---|---|
US (1) | US5714804A (de) |
EP (2) | EP0720228B1 (de) |
JP (1) | JP3955644B2 (de) |
DE (1) | DE69527344T2 (de) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6016012A (en) * | 1996-11-05 | 2000-01-18 | Cypress Semiconductor Corporation | Thin liner layer providing reduced via resistance |
US6355983B2 (en) * | 1997-05-20 | 2002-03-12 | Texas Instruments Incorporated | Surface modified interconnects |
JPH11233628A (ja) * | 1998-02-16 | 1999-08-27 | Mitsubishi Electric Corp | コンタクト構造の製造方法 |
US6870263B1 (en) * | 1998-03-31 | 2005-03-22 | Infineon Technologies Ag | Device interconnection |
US20010055868A1 (en) * | 1998-05-22 | 2001-12-27 | Madan Sudhir K. | Apparatus and method for metal layer streched conducting plugs |
US6372633B1 (en) * | 1998-07-08 | 2002-04-16 | Applied Materials, Inc. | Method and apparatus for forming metal interconnects |
US6255226B1 (en) * | 1998-12-01 | 2001-07-03 | Philips Semiconductor, Inc. | Optimized metal etch process to enable the use of aluminum plugs |
JP3408463B2 (ja) * | 1999-08-17 | 2003-05-19 | 日本電気株式会社 | 半導体装置の製造方法 |
US6261950B1 (en) * | 1999-10-18 | 2001-07-17 | Infineon Technologies Ag | Self-aligned metal caps for interlevel metal connections |
US6534866B1 (en) | 2000-04-13 | 2003-03-18 | Micron Technology, Inc. | Dual damascene interconnect |
JP2002009149A (ja) * | 2000-06-20 | 2002-01-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2005203476A (ja) * | 2004-01-14 | 2005-07-28 | Oki Electric Ind Co Ltd | 半導体装置の配線構造及びその製造方法 |
US7670946B2 (en) * | 2006-05-15 | 2010-03-02 | Chartered Semiconductor Manufacturing, Ltd. | Methods to eliminate contact plug sidewall slit |
US7704885B2 (en) * | 2007-05-24 | 2010-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for fabricating the same |
JP2009026989A (ja) * | 2007-07-20 | 2009-02-05 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2009176819A (ja) | 2008-01-22 | 2009-08-06 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP5613388B2 (ja) * | 2009-07-23 | 2014-10-22 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置の製造方法 |
JP5674433B2 (ja) * | 2010-11-17 | 2015-02-25 | ラピスセミコンダクタ株式会社 | 半導体素子の製造方法 |
CN104022071B (zh) * | 2013-02-28 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | 互连结构的形成方法 |
CN104022070B (zh) * | 2013-02-28 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 互连结构的形成方法 |
US9721889B1 (en) * | 2016-07-26 | 2017-08-01 | Globalfoundries Inc. | Middle of the line (MOL) metal contacts |
KR20180068595A (ko) * | 2016-12-14 | 2018-06-22 | 삼성전자주식회사 | 반도체 장치 |
US10186456B2 (en) * | 2017-04-20 | 2019-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming contact plugs with reduced corrosion |
US10141225B2 (en) | 2017-04-28 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gates of transistors having reduced resistivity |
KR20210066990A (ko) | 2019-11-28 | 2021-06-08 | 삼성전자주식회사 | 반도체 소자 |
KR20220045314A (ko) | 2020-10-05 | 2022-04-12 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2563048B1 (fr) | 1984-04-13 | 1986-05-30 | Efcis | Procede de realisation de contacts d'aluminium a travers une couche isolante epaisse dans un circuit integre |
US4824521A (en) * | 1987-04-01 | 1989-04-25 | Fairchild Semiconductor Corporation | Planarization of metal pillars on uneven substrates |
US5070391A (en) * | 1989-11-30 | 1991-12-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
DE69119953T2 (de) * | 1990-03-23 | 1997-01-23 | At & T Corp | Halbleiterschaltung-Leiterbahn |
JPH0438875A (ja) * | 1990-06-04 | 1992-02-10 | Toshiba Corp | 半導体装置およびその製造方法 |
DE69034137D1 (de) | 1990-10-01 | 2004-06-03 | St Microelectronics Srl | Herstellung von Kontaktanschlüssen bei der alles überdeckenden CVD-Abscheidung und Rückätzen |
US5270254A (en) * | 1991-03-27 | 1993-12-14 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit metallization with zero contact enclosure requirements and method of making the same |
JPH0791824B2 (ja) * | 1992-01-22 | 1995-10-09 | 強化土エンジニヤリング株式会社 | 地盤注入工法 |
US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
JP2756887B2 (ja) * | 1992-03-02 | 1998-05-25 | 三菱電機株式会社 | 半導体装置の導電層接続構造およびその製造方法 |
JPH05283362A (ja) * | 1992-04-03 | 1993-10-29 | Sony Corp | 多層配線の形成方法 |
JPH05347274A (ja) * | 1992-06-16 | 1993-12-27 | Sony Corp | 配線の形成方法 |
-
1995
- 1995-12-05 EP EP95308801A patent/EP0720228B1/de not_active Expired - Lifetime
- 1995-12-05 DE DE69527344T patent/DE69527344T2/de not_active Expired - Lifetime
- 1995-12-05 EP EP01100643A patent/EP1098366A1/de not_active Withdrawn
- 1995-12-25 JP JP33731195A patent/JP3955644B2/ja not_active Expired - Lifetime
-
1996
- 1996-11-14 US US08/749,083 patent/US5714804A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5714804A (en) | 1998-02-03 |
JPH08236626A (ja) | 1996-09-13 |
EP0720228B1 (de) | 2002-07-10 |
JP3955644B2 (ja) | 2007-08-08 |
EP0720228A3 (de) | 1997-02-26 |
EP1098366A1 (de) | 2001-05-09 |
DE69527344T2 (de) | 2003-02-27 |
EP0720228A2 (de) | 1996-07-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |