DE69521393D1 - Integrierte Speicherschaltungsanordnung mit Spannungserhöher - Google Patents

Integrierte Speicherschaltungsanordnung mit Spannungserhöher

Info

Publication number
DE69521393D1
DE69521393D1 DE69521393T DE69521393T DE69521393D1 DE 69521393 D1 DE69521393 D1 DE 69521393D1 DE 69521393 T DE69521393 T DE 69521393T DE 69521393 T DE69521393 T DE 69521393T DE 69521393 D1 DE69521393 D1 DE 69521393D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
memory circuit
integrated memory
voltage booster
booster
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69521393T
Other languages
English (en)
Inventor
Andrew Ferris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69521393D1 publication Critical patent/DE69521393D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
DE69521393T 1994-11-15 1995-11-09 Integrierte Speicherschaltungsanordnung mit Spannungserhöher Expired - Lifetime DE69521393D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9423038A GB9423038D0 (en) 1994-11-15 1994-11-15 An integrated circuit memory device with voltage boost

Publications (1)

Publication Number Publication Date
DE69521393D1 true DE69521393D1 (de) 2001-07-26

Family

ID=10764432

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69521393T Expired - Lifetime DE69521393D1 (de) 1994-11-15 1995-11-09 Integrierte Speicherschaltungsanordnung mit Spannungserhöher

Country Status (5)

Country Link
US (1) US5587960A (de)
EP (1) EP0714101B1 (de)
JP (1) JP2818394B2 (de)
DE (1) DE69521393D1 (de)
GB (1) GB9423038D0 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0737643B1 (de) * 1995-04-14 2000-09-13 STMicroelectronics S.r.l. Spannungserhöhungsschaltung zur Erzeugung eines annähernd konstanten Spannungspegels
KR100205007B1 (ko) * 1995-12-04 1999-06-15 윤종용 멀티-워드라인 드라이버를 갖는 반도체 메모리장치
EP0798735B1 (de) * 1996-03-29 2004-07-28 STMicroelectronics S.r.l. Zellendekodiererschaltkreis für einen nichtflüchtigen elektrisch programmierbaren Speicher und entsprechendes Verfahren
US5748554A (en) 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US5867445A (en) * 1997-10-06 1999-02-02 Vanguard International Semiconductor Corporation Local word line decoder for memory with 2 MOS devices
US5896344A (en) * 1997-10-06 1999-04-20 Vanguard International Semiconductor Corporation Local word line decoder for memory with 2 1/2 MOS devices
US5933386A (en) * 1997-12-23 1999-08-03 Mitsubishi Semiconductor America, Inc. Driving memory bitlines using boosted voltage
JP3719934B2 (ja) * 1998-04-21 2005-11-24 松下電器産業株式会社 半導体記憶装置
JP2000057766A (ja) 1998-08-11 2000-02-25 Mitsubishi Electric Corp 昇圧電圧駆動回路およびそれを用いた半導体記憶装置
US6651203B1 (en) * 1999-05-17 2003-11-18 Infineon Technologies Ag On chip programmable data pattern generator for semiconductor memories
FR2797119B1 (fr) * 1999-07-30 2001-08-31 St Microelectronics Sa Dispositif de commande d'un commutateur haute tension de type translateur
FR2797118B1 (fr) * 1999-07-30 2001-09-14 St Microelectronics Sa Dispositif de commande d'un commutateur haute tension de type translateur
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
JP4007823B2 (ja) * 2002-02-21 2007-11-14 株式会社ルネサステクノロジ 半導体記憶装置
KR100484255B1 (ko) * 2002-10-31 2005-04-22 주식회사 하이닉스반도체 감지증폭기의 동작시 노이즈가 감소된 반도체 메모리 장치
US8190808B2 (en) 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7046578B2 (en) 2004-08-23 2006-05-16 Micron Technology, Inc. Method and apparatus for memory device wordline
US7110319B2 (en) * 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
CN101331552B (zh) * 2005-12-28 2012-03-28 国际商业机器公司 用于降低电流消耗的存储器***及其方法
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5044201B2 (ja) * 2006-11-30 2012-10-10 オンセミコンダクター・トレーディング・リミテッド 半導体記憶装置
JP2009129472A (ja) * 2007-11-20 2009-06-11 Toshiba Corp 半導体記憶装置
KR20090075062A (ko) * 2008-01-03 2009-07-08 삼성전자주식회사 플로팅 바디 트랜지스터를 이용한 동적 메모리 셀을구비하는 메모리 셀 어레이를 구비하는 반도체 메모리 장치
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9275702B2 (en) * 2013-11-29 2016-03-01 The Regents Of The University Of Michigan Memory circuitry including read voltage boost
US10714166B2 (en) 2018-08-13 2020-07-14 Micron Technology, Inc. Apparatus and methods for decoding memory access addresses for access operations
JP2020149746A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体記憶装置
US10910027B2 (en) 2019-04-12 2021-02-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US10937476B2 (en) * 2019-06-24 2021-03-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US11205470B2 (en) 2020-04-20 2021-12-21 Micron Technology, Inc. Apparatuses and methods for providing main word line signal with dynamic well
US11990175B2 (en) 2022-04-01 2024-05-21 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57200997A (en) * 1981-06-03 1982-12-09 Toshiba Corp Non-volatile semiconductor memory
JPH0766666B2 (ja) * 1988-08-29 1995-07-19 三菱電機株式会社 半導体記憶装置
JPH07114077B2 (ja) * 1989-06-01 1995-12-06 三菱電機株式会社 不揮発性半導体記憶装置
JP3024687B2 (ja) * 1990-06-05 2000-03-21 三菱電機株式会社 半導体記憶装置
US5255224A (en) * 1991-12-18 1993-10-19 International Business Machines Corporation Boosted drive system for master/local word line memory architecture
JPH05182461A (ja) * 1992-01-07 1993-07-23 Nec Corp 半導体メモリ装置
US5406526A (en) * 1992-10-01 1995-04-11 Nec Corporation Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed
JP2812099B2 (ja) * 1992-10-06 1998-10-15 日本電気株式会社 半導体メモリ
JPH0798989A (ja) * 1993-09-29 1995-04-11 Sony Corp 半導体メモリの制御回路

Also Published As

Publication number Publication date
EP0714101B1 (de) 2001-06-20
JP2818394B2 (ja) 1998-10-30
EP0714101A2 (de) 1996-05-29
US5587960A (en) 1996-12-24
JPH08227593A (ja) 1996-09-03
GB9423038D0 (en) 1995-01-04
EP0714101A3 (de) 1996-06-26

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Legal Events

Date Code Title Description
8332 No legal effect for de