DE69423598D1 - Verfahren und vorrichtung zur robusten und automatischen prüfung von verzögerungsfehlern - Google Patents
Verfahren und vorrichtung zur robusten und automatischen prüfung von verzögerungsfehlernInfo
- Publication number
- DE69423598D1 DE69423598D1 DE69423598T DE69423598T DE69423598D1 DE 69423598 D1 DE69423598 D1 DE 69423598D1 DE 69423598 T DE69423598 T DE 69423598T DE 69423598 T DE69423598 T DE 69423598T DE 69423598 D1 DE69423598 D1 DE 69423598D1
- Authority
- DE
- Germany
- Prior art keywords
- signature
- robust
- testing
- point
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
- G01R31/3016—Delay or race condition test, e.g. race hazard test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
- Geophysics And Detection Of Objects (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Emergency Protection Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/096,731 US5422891A (en) | 1993-07-23 | 1993-07-23 | Robust delay fault built-in self-testing method and apparatus |
PCT/US1994/008238 WO1995003589A1 (en) | 1993-07-23 | 1994-07-21 | Robust delay fault built-in self-testing method and apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69423598D1 true DE69423598D1 (de) | 2000-04-27 |
DE69423598T2 DE69423598T2 (de) | 2000-09-14 |
Family
ID=22258821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69423598T Expired - Fee Related DE69423598T2 (de) | 1993-07-23 | 1994-07-21 | Verfahren und vorrichtung zur robusten und automatischen prüfung von verzögerungsfehlern |
Country Status (9)
Country | Link |
---|---|
US (1) | US5422891A (de) |
EP (1) | EP0663092B1 (de) |
JP (1) | JPH08502365A (de) |
KR (1) | KR950703767A (de) |
AT (1) | ATE191091T1 (de) |
AU (1) | AU7369994A (de) |
CA (1) | CA2145403C (de) |
DE (1) | DE69423598T2 (de) |
WO (1) | WO1995003589A1 (de) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE1004959A3 (nl) * | 1991-06-28 | 1993-03-02 | Bell Telephone Mfg | Werkwijze en inrichtingen voor het testen van atm-verbindingen. |
JP3124417B2 (ja) * | 1993-07-13 | 2001-01-15 | 三菱電機株式会社 | 論理シミュレーションシステム及び論理シミュレーション方法 |
JPH07114580A (ja) * | 1993-10-18 | 1995-05-02 | Fujitsu Ltd | 論理装置の遅延時間解析システム |
US5583787A (en) * | 1994-03-08 | 1996-12-10 | Motorola Inc. | Method and data processing system for determining electrical circuit path delays |
GB9417602D0 (en) * | 1994-09-01 | 1994-10-19 | Inmos Ltd | A controller for implementing scan testing |
US5974579A (en) * | 1996-09-03 | 1999-10-26 | Credence Systems Corporation | Efficient built-in self test for embedded memories with differing address spaces |
WO1998018077A1 (en) * | 1996-10-23 | 1998-04-30 | Rutgers University | Method and system for identifying tested path-delay faults |
US6018813A (en) * | 1997-04-21 | 2000-01-25 | Nec Usa, Inc. | Identification and test generation for primitive faults |
KR100292821B1 (ko) * | 1997-09-08 | 2001-06-15 | 윤종용 | 병렬 시그너츄어 압축 회로 |
US5903577A (en) * | 1997-09-30 | 1999-05-11 | Lsi Logic Corporation | Method and apparatus for analyzing digital circuits |
US6148425A (en) * | 1998-02-12 | 2000-11-14 | Lucent Technologies Inc. | Bist architecture for detecting path-delay faults in a sequential circuit |
WO1999045667A1 (en) * | 1998-03-03 | 1999-09-10 | Rutgers University | Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test |
US6308300B1 (en) * | 1999-06-04 | 2001-10-23 | Rutgers University | Test generation for analog circuits using partitioning and inverted system simulation |
JP2001042012A (ja) * | 1999-07-29 | 2001-02-16 | Mitsubishi Electric Corp | テストパターン生成装置、ループ切断方法、伝播経路切断方法、遅延故障検出方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US6760873B1 (en) * | 2000-09-28 | 2004-07-06 | Lsi Logic Corporation | Built-in self test for speed and timing margin for a source synchronous IO interface |
US6728914B2 (en) * | 2000-12-22 | 2004-04-27 | Cadence Design Systems, Inc | Random path delay testing methodology |
US20020194558A1 (en) * | 2001-04-10 | 2002-12-19 | Laung-Terng Wang | Method and system to optimize test cost and disable defects for scan and BIST memories |
JP2003233639A (ja) * | 2002-02-06 | 2003-08-22 | Mitsubishi Electric Corp | 故障検証装置、故障検証方法および故障解析手法 |
US7082558B2 (en) * | 2002-11-25 | 2006-07-25 | Texas Instruments Incorporated | Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis |
JP2005308471A (ja) * | 2004-04-20 | 2005-11-04 | Matsushita Electric Ind Co Ltd | パスディレイテスト方法 |
US20060107055A1 (en) * | 2004-11-17 | 2006-05-18 | Nesvis, Networks | Method and system to detect a data pattern of a packet in a communications network |
US8051352B2 (en) | 2006-04-27 | 2011-11-01 | Mentor Graphics Corporation | Timing-aware test generation and fault simulation |
JP5223735B2 (ja) * | 2009-03-10 | 2013-06-26 | 富士通株式会社 | メモリ試験回路及びプロセッサ |
JP5353679B2 (ja) * | 2009-12-17 | 2013-11-27 | 富士通株式会社 | 故障診断支援プログラム、および故障診断支援装置 |
US8990760B2 (en) * | 2011-08-26 | 2015-03-24 | Mentor Graphics Corporation | Cell-aware fault model generation for delay faults |
CN109388839B (zh) * | 2017-08-14 | 2023-05-30 | 龙芯中科技术股份有限公司 | 时钟***性能分析方法及装置 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58106464A (ja) * | 1981-12-21 | 1983-06-24 | Advantest Corp | グリツチ検出測定器 |
NL8303536A (nl) * | 1983-10-14 | 1985-05-01 | Philips Nv | Geintegreerde schakeling op grote schaal welke verdeeld is in isochrone gebieden, werkwijze voor het machinaal ontwerpen van zo een geintegreerde schakeling, en werkwijze voor het machinaal testen van zo een geintegreerde schakeling. |
US4688223A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4801870A (en) * | 1985-06-24 | 1989-01-31 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4687988A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4745355A (en) * | 1985-06-24 | 1988-05-17 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4635261A (en) * | 1985-06-26 | 1987-01-06 | Motorola, Inc. | On chip test system for configurable gate arrays |
US4672307A (en) * | 1985-12-20 | 1987-06-09 | University Of Southern California | Simplified delay testing for LSI circuit faults |
US4787062A (en) * | 1986-06-26 | 1988-11-22 | Ikos Systems, Inc. | Glitch detection by forcing the output of a simulated logic device to an undefined state |
JP2582250B2 (ja) * | 1986-10-03 | 1997-02-19 | 日本電信電話株式会社 | タイミング信号遅延回路装置 |
JPS63256877A (ja) * | 1987-04-14 | 1988-10-24 | Mitsubishi Electric Corp | テスト回路 |
JPS647400A (en) * | 1987-06-29 | 1989-01-11 | Hitachi Ltd | Ic tester |
US5184067A (en) * | 1988-07-12 | 1993-02-02 | Kabushiki Kaisha Toshiba | Signature compression circuit |
US5065090A (en) * | 1988-07-13 | 1991-11-12 | Cross-Check Technology, Inc. | Method for testing integrated circuits having a grid-based, "cross-check" te |
US4965474A (en) * | 1988-09-16 | 1990-10-23 | Texas Instruments Incorporated | Glitch suppression circuit |
US5051996A (en) * | 1989-03-27 | 1991-09-24 | The United States Of America As Represented By The United States Department Of Energy | Built-in-test by signature inspection (bitsi) |
US5095483A (en) * | 1989-04-28 | 1992-03-10 | International Business Machines Corporation | Signature analysis in physical modeling |
US5023875A (en) * | 1989-05-26 | 1991-06-11 | Hughes Aircraft Company | Interlaced scan fault detection system |
US5056094A (en) * | 1989-06-09 | 1991-10-08 | Texas Instruments Incorporated | Delay fault testing method and apparatus |
US5091872A (en) * | 1989-06-23 | 1992-02-25 | At&T Bell Laboratories | Apparatus and method for performing spike analysis in a logic simulator |
US5138619A (en) * | 1990-02-15 | 1992-08-11 | National Semiconductor Corporation | Built-in self test for integrated circuit memory |
JP2561164B2 (ja) * | 1990-02-26 | 1996-12-04 | 三菱電機株式会社 | 半導体集積回路 |
US5504432A (en) * | 1993-08-31 | 1996-04-02 | Hewlett-Packard Company | System and method for detecting short, opens and connected pins on a printed circuit board using automatic test equipment |
-
1993
- 1993-07-23 US US08/096,731 patent/US5422891A/en not_active Expired - Lifetime
-
1994
- 1994-07-21 WO PCT/US1994/008238 patent/WO1995003589A1/en active IP Right Grant
- 1994-07-21 DE DE69423598T patent/DE69423598T2/de not_active Expired - Fee Related
- 1994-07-21 EP EP94922668A patent/EP0663092B1/de not_active Expired - Lifetime
- 1994-07-21 AT AT94922668T patent/ATE191091T1/de active
- 1994-07-21 JP JP7505311A patent/JPH08502365A/ja active Pending
- 1994-07-21 KR KR1019950701125A patent/KR950703767A/ko active IP Right Grant
- 1994-07-21 CA CA002145403A patent/CA2145403C/en not_active Expired - Fee Related
- 1994-07-21 AU AU73699/94A patent/AU7369994A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP0663092A4 (de) | 1996-02-14 |
KR950703767A (ko) | 1995-09-20 |
CA2145403A1 (en) | 1995-02-02 |
US5422891A (en) | 1995-06-06 |
CA2145403C (en) | 2002-01-29 |
JPH08502365A (ja) | 1996-03-12 |
AU7369994A (en) | 1995-02-20 |
WO1995003589A1 (en) | 1995-02-02 |
EP0663092B1 (de) | 2000-03-22 |
ATE191091T1 (de) | 2000-04-15 |
DE69423598T2 (de) | 2000-09-14 |
EP0663092A1 (de) | 1995-07-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |