DE69326517T2 - Verfahren und Vorrichtung zur digitalen Signalverarbeitung - Google Patents

Verfahren und Vorrichtung zur digitalen Signalverarbeitung

Info

Publication number
DE69326517T2
DE69326517T2 DE69326517T DE69326517T DE69326517T2 DE 69326517 T2 DE69326517 T2 DE 69326517T2 DE 69326517 T DE69326517 T DE 69326517T DE 69326517 T DE69326517 T DE 69326517T DE 69326517 T2 DE69326517 T2 DE 69326517T2
Authority
DE
Germany
Prior art keywords
signal processing
digital signal
digital
processing
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69326517T
Other languages
English (en)
Other versions
DE69326517D1 (de
Inventor
William Kentish
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69326517D1 publication Critical patent/DE69326517D1/de
Application granted granted Critical
Publication of DE69326517T2 publication Critical patent/DE69326517T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Amplifiers (AREA)
DE69326517T 1992-09-08 1993-07-16 Verfahren und Vorrichtung zur digitalen Signalverarbeitung Expired - Fee Related DE69326517T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9218966A GB2270400B (en) 1992-09-08 1992-09-08 Digital audio mixer

Publications (2)

Publication Number Publication Date
DE69326517D1 DE69326517D1 (de) 1999-10-28
DE69326517T2 true DE69326517T2 (de) 2000-05-04

Family

ID=10721558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326517T Expired - Fee Related DE69326517T2 (de) 1992-09-08 1993-07-16 Verfahren und Vorrichtung zur digitalen Signalverarbeitung

Country Status (5)

Country Link
US (1) US5818746A (de)
EP (1) EP0587286B1 (de)
JP (1) JPH06202852A (de)
DE (1) DE69326517T2 (de)
GB (1) GB2270400B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10210443A1 (de) * 2002-03-09 2003-09-18 Bts Media Solutions Gmbh Verfahren und Vorrichtung zum Verarbeiten von Signalen

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6119141A (en) * 1998-05-06 2000-09-12 Integrated Device Technology, Inc. Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU
US7813823B2 (en) * 2006-01-17 2010-10-12 Sigmatel, Inc. Computer audio system and method
US9665341B2 (en) 2015-02-09 2017-05-30 Sonos, Inc. Synchronized audio mixing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3751650A (en) * 1971-06-28 1973-08-07 Burroughs Corp Variable length arithmetic unit
US4230908A (en) * 1979-01-22 1980-10-28 Plessey Canada Limited Telephone summing circuit
EP0098692A3 (de) * 1982-07-01 1986-04-16 Hewlett-Packard Company Einrichtung zur Addition von ersten und zweiten binären Operanden
JPS62500474A (ja) * 1985-01-31 1987-02-26 バロ−ス・コ−ポレ−シヨン 高速ｂｃｄ／バイナリ加算器
US4849921A (en) * 1985-06-19 1989-07-18 Nec Corporation Arithmetic circuit for calculating the absolute value of the difference between a pair of input signals
KR870009285A (ko) * 1986-03-25 1987-10-24 드로스트, 후흐스 세 입력신호를 논리-연결하기 위한 모듈로-2 가산기
DE3854608T2 (de) * 1987-03-04 1996-06-05 Nec Corp Vektorrechnerschaltung, welche schnell eine Berechnung auf drei Eingangsvektoren ausführen kann.
US4885792A (en) * 1988-10-27 1989-12-05 The Grass Valley Group, Inc. Audio mixer architecture using virtual gain control and switching
US5027308A (en) * 1989-02-14 1991-06-25 Intel Corporation Circuit for adding/subtracting two floating point operands
JPH038018A (ja) * 1989-06-06 1991-01-16 Toshiba Corp 符号付き絶対値加減算器
US5185714A (en) * 1989-09-19 1993-02-09 Canon Kabushiki Kaisha Arithmetic operation processing apparatus
JPH0484317A (ja) * 1990-07-27 1992-03-17 Nec Corp 算術論理演算ユニット

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10210443A1 (de) * 2002-03-09 2003-09-18 Bts Media Solutions Gmbh Verfahren und Vorrichtung zum Verarbeiten von Signalen

Also Published As

Publication number Publication date
DE69326517D1 (de) 1999-10-28
JPH06202852A (ja) 1994-07-22
EP0587286B1 (de) 1999-09-22
GB9218966D0 (en) 1992-10-21
US5818746A (en) 1998-10-06
EP0587286A1 (de) 1994-03-16
GB2270400B (en) 1996-09-18
GB2270400A (en) 1994-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee