DE69228140D1 - Verfahren und Anordnung zur Erzeugung von Übertragsignalen - Google Patents
Verfahren und Anordnung zur Erzeugung von ÜbertragsignalenInfo
- Publication number
- DE69228140D1 DE69228140D1 DE69228140T DE69228140T DE69228140D1 DE 69228140 D1 DE69228140 D1 DE 69228140D1 DE 69228140 T DE69228140 T DE 69228140T DE 69228140 T DE69228140 T DE 69228140T DE 69228140 D1 DE69228140 D1 DE 69228140D1
- Authority
- DE
- Germany
- Prior art keywords
- arrangement
- carry signals
- generating carry
- generating
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Optimization (AREA)
- Logic Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US68257591A | 1991-04-08 | 1991-04-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69228140D1 true DE69228140D1 (de) | 1999-02-25 |
DE69228140T2 DE69228140T2 (de) | 1999-08-19 |
Family
ID=24740277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69228140T Expired - Fee Related DE69228140T2 (de) | 1991-04-08 | 1992-03-20 | Verfahren und Anordnung zur Erzeugung von Übertragsignalen |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0508627B1 (de) |
JP (1) | JP3286793B2 (de) |
KR (1) | KR100256103B1 (de) |
DE (1) | DE69228140T2 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2263002B (en) * | 1992-01-06 | 1995-08-30 | Intel Corp | A parallel binary adder |
JP6454542B2 (ja) | 2014-12-26 | 2019-01-16 | Fdk株式会社 | 外付けptc素子、および筒形電池 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3346241A1 (de) * | 1983-03-31 | 1984-10-04 | Siemens AG, 1000 Berlin und 8000 München | Parallelverknuepfungsschaltung mit verkuerztem uebertragsdurchlauf |
JPS60142423A (ja) * | 1983-12-28 | 1985-07-27 | Fujitsu Ltd | 条件コ−ド生成方式 |
JPH01244531A (ja) * | 1988-03-25 | 1989-09-28 | Fujitsu Ltd | 論理回路 |
-
1992
- 1992-03-20 EP EP92302413A patent/EP0508627B1/de not_active Expired - Lifetime
- 1992-03-20 DE DE69228140T patent/DE69228140T2/de not_active Expired - Fee Related
- 1992-04-01 KR KR1019920005429A patent/KR100256103B1/ko not_active IP Right Cessation
- 1992-04-08 JP JP11430192A patent/JP3286793B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69228140T2 (de) | 1999-08-19 |
JP3286793B2 (ja) | 2002-05-27 |
EP0508627B1 (de) | 1999-01-13 |
KR920020313A (ko) | 1992-11-21 |
EP0508627A2 (de) | 1992-10-14 |
JPH0628157A (ja) | 1994-02-04 |
KR100256103B1 (ko) | 2000-05-01 |
EP0508627A3 (en) | 1994-07-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |