DE69130932D1 - Speichersystem - Google Patents

Speichersystem

Info

Publication number
DE69130932D1
DE69130932D1 DE69130932T DE69130932T DE69130932D1 DE 69130932 D1 DE69130932 D1 DE 69130932D1 DE 69130932 T DE69130932 T DE 69130932T DE 69130932 T DE69130932 T DE 69130932T DE 69130932 D1 DE69130932 D1 DE 69130932D1
Authority
DE
Germany
Prior art keywords
storage system
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130932T
Other languages
English (en)
Other versions
DE69130932T2 (de
Inventor
William J Kass
Michael R Hilley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Publication of DE69130932D1 publication Critical patent/DE69130932D1/de
Application granted granted Critical
Publication of DE69130932T2 publication Critical patent/DE69130932T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE69130932T 1990-06-06 1991-05-28 Speichersystem Expired - Fee Related DE69130932T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/534,081 US5115411A (en) 1990-06-06 1990-06-06 Dual port memory system

Publications (2)

Publication Number Publication Date
DE69130932D1 true DE69130932D1 (de) 1999-04-08
DE69130932T2 DE69130932T2 (de) 1999-08-26

Family

ID=24128638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130932T Expired - Fee Related DE69130932T2 (de) 1990-06-06 1991-05-28 Speichersystem

Country Status (4)

Country Link
US (1) US5115411A (de)
EP (1) EP0460853B1 (de)
JP (1) JPH04296958A (de)
DE (1) DE69130932T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636358A (en) * 1991-09-27 1997-06-03 Emc Corporation Method and apparatus for transferring data in a storage device including a dual-port buffer
JP2812097B2 (ja) * 1992-09-30 1998-10-15 日本電気株式会社 半導体記憶装置
US5430676A (en) * 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
US5315178A (en) * 1993-08-27 1994-05-24 Hewlett-Packard Company IC which can be used as a programmable logic cell array or as a register file
US6122706A (en) * 1993-12-22 2000-09-19 Cypress Semiconductor Corporation Dual-port content addressable memory
US5553265A (en) * 1994-10-21 1996-09-03 International Business Machines Corporation Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
US6035369A (en) * 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US5713039A (en) * 1995-12-05 1998-01-27 Advanced Micro Devices, Inc. Register file having multiple register storages for storing data from multiple data streams
US5715197A (en) 1996-07-29 1998-02-03 Xilinx, Inc. Multiport RAM with programmable data port configuration
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US5897656A (en) 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US5983303A (en) * 1997-05-27 1999-11-09 Fusion Micromedia Corporation Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method
US6052327A (en) * 1997-10-14 2000-04-18 Altera Corporation Dual-port programmable logic device variable depth and width memory array
JP2001052479A (ja) * 1999-08-06 2001-02-23 Mitsubishi Electric Corp メモリ装置
US6795889B2 (en) * 2002-01-09 2004-09-21 International Business Machines Corporation Method and apparatus for multi-path data storage and retrieval
US7111110B1 (en) 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
US7542324B1 (en) * 2006-04-17 2009-06-02 Altera Corporation FPGA equivalent input and output grid muxing on structural ASIC memory
US7761754B1 (en) * 2008-03-25 2010-07-20 Altera Corporation Techniques for testing memory circuits
US8527689B2 (en) * 2010-10-28 2013-09-03 Lsi Corporation Multi-destination direct memory access transfer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4212057A (en) * 1976-04-22 1980-07-08 General Electric Company Shared memory multi-microprocessor computer system
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
GB2021823B (en) * 1978-05-30 1983-04-27 Intel Corp Data transfer system
US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
US4868784A (en) * 1982-02-22 1989-09-19 Texas Instruments Incorporated Microcomputer with a multi-channel serial port having a single port address
JPS5998365A (ja) * 1982-11-27 1984-06-06 Shigeto Suzuki 複数同時アクセス型記憶装置
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
US4893279A (en) * 1986-03-04 1990-01-09 Advanced Micro Devices Inc. Storage arrangement having a pair of RAM memories selectively configurable for dual-access and two single-access RAMs
EP0290172A3 (de) * 1987-04-30 1991-01-16 Advanced Micro Devices, Inc. Zweirichtungsfifo mit variabler Byte-Begrenzung und Datenpfadbreitenänderung
US4815038A (en) * 1987-05-01 1989-03-21 Texas Instruments Incorporated Multiport ram memory cell
US4833649A (en) * 1987-09-08 1989-05-23 Tektronix, Inc. Multiple port random access memory
US4796232A (en) * 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US4937781A (en) * 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US4933909A (en) * 1988-12-19 1990-06-12 Bull Hn Information Systems Inc. Dual read/write register file memory
US4888741A (en) * 1988-12-27 1989-12-19 Harris Corporation Memory with cache register interface structure
US4967398A (en) * 1989-08-09 1990-10-30 Ford Motor Company Read/write random access memory with data prefetch

Also Published As

Publication number Publication date
EP0460853A2 (de) 1991-12-11
US5115411A (en) 1992-05-19
EP0460853B1 (de) 1999-03-03
EP0460853A3 (en) 1993-01-27
DE69130932T2 (de) 1999-08-26
JPH04296958A (ja) 1992-10-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee