DE69120975T2 - Verfahren zum Herstellen einer Halbleitervorrichtung - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung

Info

Publication number
DE69120975T2
DE69120975T2 DE69120975T DE69120975T DE69120975T2 DE 69120975 T2 DE69120975 T2 DE 69120975T2 DE 69120975 T DE69120975 T DE 69120975T DE 69120975 T DE69120975 T DE 69120975T DE 69120975 T2 DE69120975 T2 DE 69120975T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120975T
Other languages
English (en)
Other versions
DE69120975D1 (de
Inventor
Eiichi Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69120975D1 publication Critical patent/DE69120975D1/de
Application granted granted Critical
Publication of DE69120975T2 publication Critical patent/DE69120975T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/131Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69120975T 1990-01-12 1991-01-11 Verfahren zum Herstellen einer Halbleitervorrichtung Expired - Fee Related DE69120975T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP510890 1990-01-12

Publications (2)

Publication Number Publication Date
DE69120975D1 DE69120975D1 (de) 1996-08-29
DE69120975T2 true DE69120975T2 (de) 1996-12-19

Family

ID=11602164

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120975T Expired - Fee Related DE69120975T2 (de) 1990-01-12 1991-01-11 Verfahren zum Herstellen einer Halbleitervorrichtung

Country Status (3)

Country Link
US (1) US5183781A (de)
EP (1) EP0437371B1 (de)
DE (1) DE69120975T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
CN1038964C (zh) * 1994-05-23 1998-07-01 现代电子产业株式会社 半导体器件的接触结构及其制造方法
JP2746167B2 (ja) * 1995-01-25 1998-04-28 日本電気株式会社 半導体装置の製造方法
US5624870A (en) * 1995-03-16 1997-04-29 United Microelectronics Corporation Method of contact planarization
KR0144909B1 (ko) * 1995-03-21 1998-07-01 김광호 비휘발성 메모리 장치의 셀 어레이 레이아웃 방법
US5587338A (en) * 1995-04-27 1996-12-24 Vanguard International Semiconductor Corporation Polysilicon contact stud process
US5534460A (en) * 1995-04-27 1996-07-09 Vanguard International Semiconductor Corp. Optimized contact plug process
US5599736A (en) * 1995-06-28 1997-02-04 Vanguard International Semiconductor Corporation Fabrication method for polysilicon contact plugs
US5856700A (en) * 1996-05-08 1999-01-05 Harris Corporation Semiconductor device with doped semiconductor and dielectric trench sidewall layers
US6440837B1 (en) * 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US6563156B2 (en) 2001-03-15 2003-05-13 Micron Technology, Inc. Memory elements and methods for making same
KR100475122B1 (ko) * 2002-12-20 2005-03-10 삼성전자주식회사 실리콘 접촉저항을 개선할 수 있는 반도체 소자 형성방법
CN102468222A (zh) * 2010-11-16 2012-05-23 上海华虹Nec电子有限公司 射频ldmos器件中源衬接触柱的实现方法
JP2014222699A (ja) 2013-05-13 2014-11-27 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置の製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010718A (ja) * 1983-06-30 1985-01-19 Nec Corp 半導体装置の製造方法
JPS61222225A (ja) * 1985-03-28 1986-10-02 Fujitsu Ltd 半導体装置の製造方法
JPS63181423A (ja) * 1987-01-23 1988-07-26 Toshiba Corp 半導体装置の製造方法
US4728391A (en) * 1987-05-11 1988-03-01 Motorola Inc. Pedestal transistors and method of production thereof
JPS6465625A (en) * 1987-09-07 1989-03-10 Alps Electric Co Ltd Optical type coordinate input device
JPH025525A (ja) * 1988-06-24 1990-01-10 Nec Corp 半導体基板のエッチング方法
JPH02108541A (ja) * 1988-10-18 1990-04-20 Nec Corp 印刷装置等の定着器

Also Published As

Publication number Publication date
EP0437371A2 (de) 1991-07-17
DE69120975D1 (de) 1996-08-29
US5183781A (en) 1993-02-02
EP0437371B1 (de) 1996-07-24
EP0437371A3 (en) 1992-06-10

Similar Documents

Publication Publication Date Title
DE69133316D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69030229D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69033736D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69022087T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE69031543D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE68917995T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69031184T2 (de) Verfahren zum Herstellen einer Halbleiterbauelement-Packung
DE68919549D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68911621D1 (de) Verfahren zum Herstellen einer Einrichtung.
DE69028964T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE68920094D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68926656T2 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE68906034T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE69120975D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69506646T2 (de) Verfahren zum Herstellen einer Halbleitereinrichtung
DE69022710D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE3883856T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68922085D1 (de) Halbleiteranordung und Verfahren zum Herstellen einer Halbleiteranordung.
DE3888457D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69018884T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69116592T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE69229288D1 (de) Verfahren zum Herstellen einer Halbleiterspeicheranordnung
DE69116938D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE69128326D1 (de) Ein Verfahren zum Herstellen einer Halbleiteranordnung
DE69429636D1 (de) Verfahren zum Herstellen einer Halbleiteranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee