DE69120488D1 - Verfahren zur Herstellung eines Isolierungsbereiches von Halbleiterbauelementen - Google Patents

Verfahren zur Herstellung eines Isolierungsbereiches von Halbleiterbauelementen

Info

Publication number
DE69120488D1
DE69120488D1 DE69120488T DE69120488T DE69120488D1 DE 69120488 D1 DE69120488 D1 DE 69120488D1 DE 69120488 T DE69120488 T DE 69120488T DE 69120488 T DE69120488 T DE 69120488T DE 69120488 D1 DE69120488 D1 DE 69120488D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor components
isolation area
isolation
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69120488T
Other languages
English (en)
Other versions
DE69120488T2 (de
Inventor
Akio Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69120488D1 publication Critical patent/DE69120488D1/de
Application granted granted Critical
Publication of DE69120488T2 publication Critical patent/DE69120488T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69120488T 1990-09-18 1991-09-18 Verfahren zur Herstellung eines Isolierungsbereiches von Halbleiterbauelementen Expired - Lifetime DE69120488T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2249724A JPH04127433A (ja) 1990-09-18 1990-09-18 半導体素子分離領域の形成方法

Publications (2)

Publication Number Publication Date
DE69120488D1 true DE69120488D1 (de) 1996-08-01
DE69120488T2 DE69120488T2 (de) 1996-12-12

Family

ID=17197257

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120488T Expired - Lifetime DE69120488T2 (de) 1990-09-18 1991-09-18 Verfahren zur Herstellung eines Isolierungsbereiches von Halbleiterbauelementen

Country Status (5)

Country Link
US (1) US5173444A (de)
EP (1) EP0476988B1 (de)
JP (1) JPH04127433A (de)
KR (1) KR960006432B1 (de)
DE (1) DE69120488T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297130B1 (en) * 1991-04-30 2001-10-02 Texas Instruments Incorporated Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS isolation methods
KR950004972B1 (ko) * 1992-10-13 1995-05-16 현대전자산업주식회사 반도체 장치의 필드산화막 형성 방법
KR960005553B1 (ko) * 1993-03-31 1996-04-26 현대전자산업주식회사 필드산화막 형성 방법
SE501079C2 (sv) * 1993-04-16 1994-11-07 Asea Brown Boveri Metod för etsning av kiselområden på isolerande substrat
KR960006976B1 (ko) * 1993-05-21 1996-05-25 현대전자산업주식회사 반도체 소자의 필드 산화막 제조 방법
KR960011861B1 (ko) * 1993-06-10 1996-09-03 삼성전자 주식회사 반도체장치의 소자 분리 방법
US6310384B1 (en) 1993-07-02 2001-10-30 Hitachi, Ltd. Low stress semiconductor devices with thermal oxide isolation
KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
US5374585A (en) * 1994-05-09 1994-12-20 Motorola, Inc. Process for forming field isolation
JPH0817813A (ja) * 1994-06-24 1996-01-19 Nec Corp 半導体装置の製造方法
JP3249892B2 (ja) * 1994-11-28 2002-01-21 三菱電機株式会社 Ｓｏｉ構造を有する半導体装置の製造方法
KR100186514B1 (ko) * 1996-06-10 1999-04-15 문정환 반도체 소자의 격리영역 형성방법
KR980006089A (ko) * 1996-06-29 1998-03-30 김주용 반도체 소자의 소자분리막 제조방법
KR100189733B1 (ko) * 1996-07-22 1999-06-01 구본준 반도체장치의 소자분리막 형성방법
US5643824A (en) * 1996-07-29 1997-07-01 Vanguard International Semiconductor Corporation Method of forming nitride sidewalls having spacer feet in a locos process
WO1998008252A1 (en) * 1996-08-22 1998-02-26 Advanced Micro Devices, Inc. Method for differential fieldox growth
KR100219043B1 (ko) * 1996-12-20 1999-09-01 김영환 반도체 장치의 소자분리막 형성 방법
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
KR100232899B1 (ko) * 1997-06-02 1999-12-01 김영환 반도체소자의 소자분리막 제조방법
US5804492A (en) * 1997-06-11 1998-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating an isolation region for semiconductor device
KR100235950B1 (ko) * 1997-06-26 1999-12-15 김영환 반도체 소자의 필드 산화막 제조방법
KR100422960B1 (ko) * 1997-06-28 2004-06-12 주식회사 하이닉스반도체 반도체소자의 소자분리절연막 형성방법
US5891787A (en) * 1997-09-04 1999-04-06 Advanced Micro Devices, Inc. Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure
US6444539B1 (en) * 1998-05-20 2002-09-03 Advanced Micro Devices, Inc. Method for producing a shallow trench isolation filled with thermal oxide
JP2000031273A (ja) * 1998-07-13 2000-01-28 Nec Corp 半導体装置およびその製造方法
US6406987B1 (en) 1998-09-08 2002-06-18 Taiwan Semiconductor Manufacturing Company Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions
US20040259323A1 (en) * 1999-05-11 2004-12-23 Wei-Kang King Semiconductor structure containing field oxide and method for fabricating the same
JP2002134604A (ja) * 2000-10-27 2002-05-10 Oki Electric Ind Co Ltd 半導体装置における素子分離領域の形成方法
CN102931125A (zh) * 2011-08-10 2013-02-13 无锡华润上华科技有限公司 半导体器件及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164550A (en) * 1980-05-21 1981-12-17 Fujitsu Ltd Manufacture of semiconductor device
JPS61251145A (ja) * 1985-04-30 1986-11-08 Fujitsu Ltd 半導体装置の製造方法
JPS63152155A (ja) * 1986-12-16 1988-06-24 Sharp Corp 半導体装置の製造方法
EP0280587A1 (de) * 1987-01-20 1988-08-31 Thomson Components-Mostek Corporation VLSI-Verfahren unter Verwendung einer Maske mit Distanzstücken
DE3865058D1 (de) * 1987-02-24 1991-10-31 Sgs Thomson Microelectronics Isolationsverfahren mit einer durch eine schutzschicht aus oxid geschuetzten zwischenschicht.
DE3738643A1 (de) * 1987-11-13 1989-05-24 Siemens Ag Verfahren zum herstellen von isolationsschichten in hochintegrierten halbleiterschaltungen
JPH0210729A (ja) * 1988-06-29 1990-01-16 Kawasaki Steel Corp フィールド絶縁膜の形成方法
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions

Also Published As

Publication number Publication date
KR960006432B1 (ko) 1996-05-15
EP0476988A1 (de) 1992-03-25
JPH04127433A (ja) 1992-04-28
US5173444A (en) 1992-12-22
EP0476988B1 (de) 1996-06-26
DE69120488T2 (de) 1996-12-12

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Legal Events

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8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN

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