DE69025647D1 - Verfahren zur Herstellung von komplementären NPN/PNP hoher Spannung - Google Patents

Verfahren zur Herstellung von komplementären NPN/PNP hoher Spannung

Info

Publication number
DE69025647D1
DE69025647D1 DE69025647T DE69025647T DE69025647D1 DE 69025647 D1 DE69025647 D1 DE 69025647D1 DE 69025647 T DE69025647 T DE 69025647T DE 69025647 T DE69025647 T DE 69025647T DE 69025647 D1 DE69025647 D1 DE 69025647D1
Authority
DE
Germany
Prior art keywords
pnp
production
high voltage
complementary high
voltage npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025647T
Other languages
English (en)
Other versions
DE69025647T2 (de
Inventor
Dean Jennings
Matthew Buynoski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69025647D1 publication Critical patent/DE69025647D1/de
Publication of DE69025647T2 publication Critical patent/DE69025647T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE69025647T 1989-06-06 1990-06-02 Verfahren zur Herstellung von komplementären NPN/PNP hoher Spannung Expired - Fee Related DE69025647T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/361,171 US4910160A (en) 1989-06-06 1989-06-06 High voltage complementary NPN/PNP process

Publications (2)

Publication Number Publication Date
DE69025647D1 true DE69025647D1 (de) 1996-04-11
DE69025647T2 DE69025647T2 (de) 1996-10-02

Family

ID=23420940

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025647T Expired - Fee Related DE69025647T2 (de) 1989-06-06 1990-06-02 Verfahren zur Herstellung von komplementären NPN/PNP hoher Spannung

Country Status (5)

Country Link
US (1) US4910160A (de)
EP (1) EP0401716B1 (de)
JP (1) JP2934484B2 (de)
KR (1) KR0143412B1 (de)
DE (1) DE69025647T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5529939A (en) * 1986-09-26 1996-06-25 Analog Devices, Incorporated Method of making an integrated circuit with complementary isolated bipolar transistors
JPH06101540B2 (ja) * 1989-05-19 1994-12-12 三洋電機株式会社 半導体集積回路の製造方法
JP2783888B2 (ja) * 1990-02-05 1998-08-06 松下電器産業株式会社 半導体装置およびその製造方法
JP2503733B2 (ja) * 1990-06-22 1996-06-05 三菱電機株式会社 半導体装置の製造方法
US4999309A (en) * 1990-07-12 1991-03-12 National Semiconductor Corporation Aluminum-implant leakage reduction
JP2748988B2 (ja) * 1991-03-13 1998-05-13 三菱電機株式会社 半導体装置とその製造方法
US5128272A (en) * 1991-06-18 1992-07-07 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
FR2678430B1 (fr) * 1991-06-28 1993-10-29 Sgs Thomson Microelectronics Sa Diode a avalanche dans un circuit integre bipolaire.
US5340752A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method for forming a bipolar transistor using doped SOG
JPH09500760A (ja) * 1993-07-12 1997-01-21 ナショナル・セミコンダクター・コーポレイション ヒ素注入エミッタを有する半導体デバイスの製造プロセス
US5885880A (en) * 1994-09-19 1999-03-23 Sony Corporation Bipolar transistor device and method for manufacturing the same
US5719423A (en) * 1995-08-31 1998-02-17 Texas Instruments Incorporated Isolated power transistor
DE69531783T2 (de) * 1995-10-09 2004-07-15 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme Herstellungsverfahren für Leistungsanordnung mit Schutzring
DE69533134T2 (de) 1995-10-30 2005-07-07 Stmicroelectronics S.R.L., Agrate Brianza Leistungsbauteil hoher Dichte in MOS-Technologie
EP0772242B1 (de) 1995-10-30 2006-04-05 STMicroelectronics S.r.l. Leistungsbauteil in MOS-Technologie mit einer einzelnen kritischen Grösse
JP3409548B2 (ja) 1995-12-12 2003-05-26 ソニー株式会社 半導体装置の製造方法
US5614433A (en) * 1995-12-18 1997-03-25 International Business Machines Corporation Method of fabricating low leakage SOI integrated circuits
US7804115B2 (en) * 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) * 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
DE69839439D1 (de) 1998-05-26 2008-06-19 St Microelectronics Srl MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6268282B1 (en) 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6828683B2 (en) * 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7235499B1 (en) * 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
EP1061572A1 (de) * 1999-06-16 2000-12-20 STMicroelectronics S.r.l. Integrierte Struktur für Radiofrequenzanwendungen
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
US6440860B1 (en) * 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
US6921708B1 (en) * 2000-04-13 2005-07-26 Micron Technology, Inc. Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean
KR100386340B1 (ko) * 2001-01-08 2003-06-02 주식회사 에스제이하이테크 다중격막 진공차폐 커버씰
US6660608B1 (en) 2002-02-25 2003-12-09 Advanced Micro Devices, Inc. Method for manufacturing CMOS device having low gate resistivity using aluminum implant
US6815801B2 (en) * 2003-02-28 2004-11-09 Texas Instrument Incorporated Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer
JP2007095827A (ja) * 2005-09-27 2007-04-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5048242B2 (ja) * 2005-11-30 2012-10-17 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP2008042013A (ja) * 2006-08-08 2008-02-21 Sanyo Electric Co Ltd 半導体装置の製造方法
WO2009029900A1 (en) * 2007-08-31 2009-03-05 Applied Materials, Inc. Improved methods of emitter formation in solar cells
US20100304527A1 (en) * 2009-03-03 2010-12-02 Peter Borden Methods of thermal processing a solar cell
CN107039510B (zh) * 2017-04-20 2020-05-05 重庆中科渝芯电子有限公司 一种纵向高压功率双极结型晶体管及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL145396B (nl) * 1966-10-21 1975-03-17 Philips Nv Werkwijze ter vervaardiging van een geintegreerde halfgeleiderinrichting en geintegreerde halfgeleiderinrichting, vervaardigd volgens de werkwijze.
US4038680A (en) * 1972-12-29 1977-07-26 Sony Corporation Semiconductor integrated circuit device
US3901735A (en) * 1973-09-10 1975-08-26 Nat Semiconductor Corp Integrated circuit device and method utilizing ion implanted and up diffusion for isolated region
DE2351985A1 (de) * 1973-10-17 1975-04-30 Itt Ind Gmbh Deutsche Planardiffusionsverfahren zum herstellen einer monolithisch integrierten festkoerperschaltung
CA1047652A (en) * 1975-07-31 1979-01-30 National Semiconductor Corporation Monolithic integrated circuit transistor having very low collector resistance
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
EP0030147B1 (de) * 1979-11-29 1983-05-11 Kabushiki Kaisha Toshiba Verfahren zur Herstellung einer integrierten Halbleiter-Schaltung
US4534806A (en) * 1979-12-03 1985-08-13 International Business Machines Corporation Method for manufacturing vertical PNP transistor with shallow emitter
US4299024A (en) * 1980-02-25 1981-11-10 Harris Corporation Fabrication of complementary bipolar transistors and CMOS devices with poly gates
EP0065346A3 (de) * 1981-05-20 1983-08-31 Reliance Electric Company Halbleiter-Schaltungsanordnung
US4512816A (en) * 1982-02-26 1985-04-23 National Semiconductor Corporation High-density IC isolation technique capacitors
US4553044A (en) * 1983-05-11 1985-11-12 National Semiconductor Corporation Integrated circuit output driver stage
JPS60194558A (ja) * 1984-03-16 1985-10-03 Hitachi Ltd 半導体装置の製造方法
US4719185A (en) * 1986-04-28 1988-01-12 International Business Machines Corporation Method of making shallow junction complementary vertical bipolar transistor pair

Also Published As

Publication number Publication date
EP0401716A2 (de) 1990-12-12
JP2934484B2 (ja) 1999-08-16
US4910160A (en) 1990-03-20
JPH0334364A (ja) 1991-02-14
DE69025647T2 (de) 1996-10-02
KR0143412B1 (ko) 1998-07-01
EP0401716A3 (de) 1992-07-08
EP0401716B1 (de) 1996-03-06

Similar Documents

Publication Publication Date Title
DE69025647D1 (de) Verfahren zur Herstellung von komplementären NPN/PNP hoher Spannung
DE69010857D1 (de) Verfahren zur Herstellung dünner Schichten von hoher Reinheit.
DE69132176D1 (de) Verfahren zur Herstellung von Elektroden
DE69207705D1 (de) Verfahren zur Herstellung von Äthylacetat
ATE102617T1 (de) Verfahren zur herstellung von zyklischen estern hoher reinheit.
DE69125233D1 (de) Verfahren zur Herstellung von gedruckten Schaltungen
DE59108655D1 (de) Verfahren zur Herstellung von Celluloseformkörpern
DE69118743D1 (de) Verfahren zur Herstellung von Mikrokapseln
DE59010596D1 (de) Verfahren zur Herstellung von Polycarbonat-Formmassen
DE69317519D1 (de) Verfahren zur Herstellung von kristallinen Mikrohohlkugeln
DE69219393D1 (de) Verfahren zur Herstellung von Mikrokapseln
DE69110590D1 (de) Verfahren zur Herstellung von Anilin von hoher Reinheit.
DE69120167D1 (de) Verbessertes Verfahren zur Herstellung von Polyglycidylnitraten
DE69101337D1 (de) Verfahren zur Herstellung von Anilin hoher Reinheit.
DE69030225D1 (de) Verfahren zur Herstellung von BiMOS-Schaltungen mit hoher Leistung
DE69020172D1 (de) Verfahren zur Herstellung von epsilon-Caprolactam.
DE69009351D1 (de) Verfahren zur Herstellung von O-Dichtungen.
DE69028450D1 (de) Verfahren zur Herstellung von polykristallinen Siliziumkontakten
DE69217346D1 (de) Verfahren zur Herstellung von Mikroleuchtkörpern
DE69213916D1 (de) Verfahren zur Herstellung von L-Ambrox
DE69032464D1 (de) Verfahren zur Herstellung von Photolackmustern
DE69314142D1 (de) Verfahren zur Herstellung von Keramikteilen
DE69310232D1 (de) Verfahren zur Herstellung von Organomonochlorsilan
DE69017345D1 (de) Verfahren zur Herstellung von Cellobiose.
DE69133173D1 (de) Verfahren zur Herstellung von Knollen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee