DE68928519D1 - Verfahren und Vorrichtung zur Vorhersage der richtigen Durchführung der Übersetzungen von virtuellen in physikalische Adressen - Google Patents
Verfahren und Vorrichtung zur Vorhersage der richtigen Durchführung der Übersetzungen von virtuellen in physikalische AdressenInfo
- Publication number
- DE68928519D1 DE68928519D1 DE68928519T DE68928519T DE68928519D1 DE 68928519 D1 DE68928519 D1 DE 68928519D1 DE 68928519 T DE68928519 T DE 68928519T DE 68928519 T DE68928519 T DE 68928519T DE 68928519 D1 DE68928519 D1 DE 68928519D1
- Authority
- DE
- Germany
- Prior art keywords
- translations
- predicting
- virtual
- physical addresses
- correct implementation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/655—Same page detection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/224,443 US5179674A (en) | 1988-07-25 | 1988-07-25 | Method and apparatus for predicting valid performance of virtual-address to physical-address translations |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68928519D1 true DE68928519D1 (de) | 1998-02-12 |
DE68928519T2 DE68928519T2 (de) | 1998-08-27 |
Family
ID=22840705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68928519T Expired - Fee Related DE68928519T2 (de) | 1988-07-25 | 1989-07-20 | Verfahren und Vorrichtung zur Vorhersage der richtigen Durchführung der Übersetzungen von virtuellen in physikalische Adressen |
Country Status (6)
Country | Link |
---|---|
US (2) | US5179674A (de) |
EP (1) | EP0352632B1 (de) |
JP (1) | JPH0240744A (de) |
KR (1) | KR930002328B1 (de) |
CA (1) | CA1313269C (de) |
DE (1) | DE68928519T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2503702B2 (ja) * | 1989-12-19 | 1996-06-05 | 日本電気株式会社 | アドレス変換装置 |
CA2045789A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Granularity hint for translation buffer in high performance processor |
US5530881A (en) * | 1991-06-06 | 1996-06-25 | Hitachi, Ltd. | Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs |
US5333291A (en) * | 1991-06-14 | 1994-07-26 | International Business Machines Corporation | Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination |
US5437043A (en) * | 1991-11-20 | 1995-07-25 | Hitachi, Ltd. | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers |
US5392410A (en) * | 1992-04-30 | 1995-02-21 | International Business Machines Corporation | History table for prediction of virtual address translation for cache access |
US5729723A (en) * | 1992-11-16 | 1998-03-17 | Hitachi, Ltd. | Data processing unit |
JP2725546B2 (ja) * | 1992-12-07 | 1998-03-11 | 株式会社日立製作所 | デ−タ処理装置 |
JP3304444B2 (ja) * | 1992-11-30 | 2002-07-22 | 富士通株式会社 | ベクトル処理装置 |
US5606683A (en) * | 1994-01-28 | 1997-02-25 | Quantum Effect Design, Inc. | Structure and method for virtual-to-physical address translation in a translation lookaside buffer |
US5890222A (en) * | 1995-01-04 | 1999-03-30 | International Business Machines Corporation | Method and system for addressing registers in a data processing unit in an indirect addressing mode |
US5832533A (en) * | 1995-01-04 | 1998-11-03 | International Business Machines Corporation | Method and system for addressing registers in a data processing unit in an indexed addressing mode |
US5887183A (en) * | 1995-01-04 | 1999-03-23 | International Business Machines Corporation | Method and system in a data processing system for loading and storing vectors in a plurality of modes |
US5680338A (en) * | 1995-01-04 | 1997-10-21 | International Business Machines Corporation | Method and system for vector processing utilizing selected vector elements |
US5752275A (en) * | 1995-03-31 | 1998-05-12 | Intel Corporation | Translation look-aside buffer including a single page size translation unit |
US5918250A (en) * | 1995-05-05 | 1999-06-29 | Intel Corporation | Method and apparatus for preloading default address translation attributes |
US5893930A (en) * | 1996-07-12 | 1999-04-13 | International Business Machines Corporation | Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer |
US5918251A (en) * | 1996-12-23 | 1999-06-29 | Intel Corporation | Method and apparatus for preloading different default address translation attributes |
US6138225A (en) * | 1997-12-24 | 2000-10-24 | Intel Corporation | Address translation system having first and second translation look aside buffers |
US6175908B1 (en) | 1998-04-30 | 2001-01-16 | Advanced Micro Devices, Inc. | Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte |
US6141745A (en) * | 1998-04-30 | 2000-10-31 | Advanced Micro Devices, Inc. | Functional bit identifying a prefix byte via a particular state regardless of type of instruction |
US6189094B1 (en) * | 1998-05-27 | 2001-02-13 | Arm Limited | Recirculating register file |
GB2339037B (en) * | 1998-07-03 | 2002-11-20 | Advanced Risc Mach Ltd | Memory address translation in a data processing system |
US6266759B1 (en) * | 1998-12-14 | 2001-07-24 | Cray, Inc. | Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor |
US6625720B1 (en) * | 1999-08-17 | 2003-09-23 | Nec Electronics, Inc. | System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs |
US6813701B1 (en) * | 1999-08-17 | 2004-11-02 | Nec Electronics America, Inc. | Method and apparatus for transferring vector data between memory and a register file |
US6665749B1 (en) * | 1999-08-17 | 2003-12-16 | Nec Electronics, Inc. | Bus protocol for efficiently transferring vector data |
US6513107B1 (en) * | 1999-08-17 | 2003-01-28 | Nec Electronics, Inc. | Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page |
US9311094B2 (en) * | 2011-01-21 | 2016-04-12 | Apple Inc. | Predicting a pattern in addresses for a memory-accessing instruction when processing vector instructions |
EP2757468A1 (de) * | 2013-01-22 | 2014-07-23 | Siemens Aktiengesellschaft | Vorrichtung und Verfahren zur Verwaltung eines Softwareentwicklungs- und -wartungssystems |
CN108334291B (zh) * | 2018-03-07 | 2021-05-18 | 成都创信特电子技术有限公司 | 建立移动终端可信环境的方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1059639A (en) * | 1975-03-26 | 1979-07-31 | Garvin W. Patterson | Instruction look ahead having prefetch concurrency and pipe line features |
US4541046A (en) * | 1981-03-25 | 1985-09-10 | Hitachi, Ltd. | Data processing system including scalar data processor and vector data processor |
US4462074A (en) * | 1981-11-19 | 1984-07-24 | Codex Corporation | Do loop circuit |
US4463422A (en) * | 1982-07-12 | 1984-07-31 | Csp, Inc. | Method of processing an iterative program loop |
JPS60156151A (ja) * | 1983-12-23 | 1985-08-16 | Nec Corp | メモリアクセス制御装置 |
FR2561429B1 (fr) * | 1984-03-13 | 1986-09-19 | Trt Telecom Radio Electr | Dispositif d'adressage pour fournir a une memoire des codes d'adresse |
US4620275A (en) * | 1984-06-20 | 1986-10-28 | Wallach Steven J | Computer system |
US4727483A (en) * | 1984-08-15 | 1988-02-23 | Tektronix, Inc. | Loop control system for digital processing apparatus |
JPH0652511B2 (ja) * | 1984-12-14 | 1994-07-06 | 株式会社日立製作所 | 情報処理装置のアドレス変換方式 |
JPH0656594B2 (ja) * | 1985-05-07 | 1994-07-27 | 株式会社日立製作所 | ベクトルプロセツサ |
JPH0622035B2 (ja) * | 1985-11-13 | 1994-03-23 | 株式会社日立製作所 | ベクトル処理装置 |
US4811215A (en) * | 1986-12-12 | 1989-03-07 | Intergraph Corporation | Instruction execution accelerator for a pipelined digital machine with virtual memory |
JPS63180171A (ja) * | 1987-01-21 | 1988-07-25 | Fujitsu Ltd | 情報処理装置 |
US4926317A (en) * | 1987-07-24 | 1990-05-15 | Convex Computer Corporation | Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses |
US5179709A (en) * | 1989-01-13 | 1993-01-12 | International Business Machines Corporation | Look ahead bus transfer request |
-
1988
- 1988-07-25 US US07/224,443 patent/US5179674A/en not_active Expired - Lifetime
-
1989
- 1989-05-10 CA CA000599270A patent/CA1313269C/en not_active Expired - Fee Related
- 1989-05-15 JP JP1121298A patent/JPH0240744A/ja active Pending
- 1989-07-20 DE DE68928519T patent/DE68928519T2/de not_active Expired - Fee Related
- 1989-07-20 EP EP89113323A patent/EP0352632B1/de not_active Expired - Lifetime
- 1989-07-25 KR KR1019890010501A patent/KR930002328B1/ko not_active IP Right Cessation
-
1992
- 1992-09-10 US US07/943,165 patent/US5319791A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0352632A2 (de) | 1990-01-31 |
DE68928519T2 (de) | 1998-08-27 |
CA1313269C (en) | 1993-01-26 |
EP0352632B1 (de) | 1998-01-07 |
KR900002187A (ko) | 1990-02-28 |
KR930002328B1 (ko) | 1993-03-29 |
US5319791A (en) | 1994-06-07 |
US5179674A (en) | 1993-01-12 |
EP0352632A3 (de) | 1990-10-24 |
JPH0240744A (ja) | 1990-02-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |