DE68927492D1 - Verfahren und Vorrichtung zur gleichzeitigen Verteilung von Befehlen an mehrere funktionelle Einheiten - Google Patents
Verfahren und Vorrichtung zur gleichzeitigen Verteilung von Befehlen an mehrere funktionelle EinheitenInfo
- Publication number
- DE68927492D1 DE68927492D1 DE68927492T DE68927492T DE68927492D1 DE 68927492 D1 DE68927492 D1 DE 68927492D1 DE 68927492 T DE68927492 T DE 68927492T DE 68927492 T DE68927492 T DE 68927492T DE 68927492 D1 DE68927492 D1 DE 68927492D1
- Authority
- DE
- Germany
- Prior art keywords
- commands
- functional units
- several functional
- simultaneous distribution
- simultaneous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/255,105 US5051885A (en) | 1988-10-07 | 1988-10-07 | Data processing system for concurrent dispatch of instructions to multiple functional units |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68927492D1 true DE68927492D1 (de) | 1997-01-09 |
DE68927492T2 DE68927492T2 (de) | 1997-04-03 |
Family
ID=22966857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68927492T Expired - Lifetime DE68927492T2 (de) | 1988-10-07 | 1989-10-06 | Verfahren und Vorrichtung zur gleichzeitigen Verteilung von Befehlen an mehrere funktionelle Einheiten |
Country Status (4)
Country | Link |
---|---|
US (1) | US5051885A (de) |
EP (1) | EP0363222B1 (de) |
JP (1) | JP2864421B2 (de) |
DE (1) | DE68927492T2 (de) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0365322A3 (de) * | 1988-10-19 | 1991-11-27 | Hewlett-Packard Company | Verfahren und Vorrichtung zur Ausnahmenbehandlung in Fliessbandprozessoren mit unterschiedlicher Befehlspipelinetiefe |
EP0378415A3 (de) * | 1989-01-13 | 1991-09-25 | International Business Machines Corporation | Verteilungsmechanismus für mehrere Befehle |
JP2835103B2 (ja) * | 1989-11-01 | 1998-12-14 | 富士通株式会社 | 命令指定方法及び命令実行方式 |
CA2037708C (en) * | 1990-05-04 | 1998-01-20 | Richard J. Eickemeyer | General purpose compound apparatus for instruction-level parallel processors |
DE69130588T2 (de) * | 1990-05-29 | 1999-05-27 | National Semiconductor Corp., Santa Clara, Calif. | Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür |
JP2771683B2 (ja) * | 1990-07-17 | 1998-07-02 | 三菱電機株式会社 | 並列処理方式 |
US5163139A (en) * | 1990-08-29 | 1992-11-10 | Hitachi America, Ltd. | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions |
EP0477598A2 (de) * | 1990-09-26 | 1992-04-01 | Siemens Aktiengesellschaft | Befehlswerk für einen n Prozessorelemente aufweisenden Prozessor |
DE69231011T2 (de) * | 1991-02-08 | 2000-09-28 | Fujitsu Ltd., Kawasaki | Cachespeicher zur Verarbeitung von Befehlsdaten und Datenprozessor mit demselben |
JP2925818B2 (ja) * | 1991-04-05 | 1999-07-28 | 株式会社東芝 | 並列処理制御装置 |
DE69327688T2 (de) | 1992-08-12 | 2000-09-07 | Advanced Micro Devices, Inc. | Befehlsdecoder |
US5617549A (en) * | 1992-10-06 | 1997-04-01 | Hewlett-Packard Co | System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer |
US5410721A (en) * | 1992-12-24 | 1995-04-25 | Motorola, Inc. | System and method for incrementing a program counter |
US5721854A (en) * | 1993-11-02 | 1998-02-24 | International Business Machines Corporation | Method and apparatus for dynamic conversion of computer instructions |
EP1186995B1 (de) * | 1993-11-05 | 2003-09-03 | Intergraph Corporation | Befehlsspeicher mit assoziativem Kreuzschienenschalter |
US6360313B1 (en) | 1993-11-05 | 2002-03-19 | Intergraph Corporation | Instruction cache associative crossbar switch |
US5510934A (en) * | 1993-12-15 | 1996-04-23 | Silicon Graphics, Inc. | Memory system including local and global caches for storing floating point and integer data |
JP3462245B2 (ja) * | 1993-12-22 | 2003-11-05 | 株式会社リコー | 中央演算処理装置 |
US5590351A (en) * | 1994-01-21 | 1996-12-31 | Advanced Micro Devices, Inc. | Superscalar execution unit for sequential instruction pointer updates and segment limit checks |
US5559975A (en) * | 1994-06-01 | 1996-09-24 | Advanced Micro Devices, Inc. | Program counter update mechanism |
US5590358A (en) * | 1994-09-16 | 1996-12-31 | Philips Electronics North America Corporation | Processor with word-aligned branch target in a byte-oriented instruction set |
US5640526A (en) * | 1994-12-21 | 1997-06-17 | International Business Machines Corporation | Superscaler instruction pipeline having boundary indentification logic for variable length instructions |
US6006324A (en) * | 1995-01-25 | 1999-12-21 | Advanced Micro Devices, Inc. | High performance superscalar alignment unit |
US5867726A (en) * | 1995-05-02 | 1999-02-02 | Hitachi, Ltd. | Microcomputer |
JP3598589B2 (ja) * | 1995-06-28 | 2004-12-08 | 株式会社日立製作所 | プロセッサ |
US5761469A (en) * | 1995-08-15 | 1998-06-02 | Sun Microsystems, Inc. | Method and apparatus for optimizing signed and unsigned load processing in a pipelined processor |
US5850563A (en) * | 1995-09-11 | 1998-12-15 | International Business Machines Corporation | Processor and method for out-of-order completion of floating-point operations during load/store multiple operations |
US5761105A (en) * | 1995-09-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Reservation station including addressable constant store for a floating point processing unit |
US5878266A (en) * | 1995-09-26 | 1999-03-02 | Advanced Micro Devices, Inc. | Reservation station for a floating point processing unit |
JP3535354B2 (ja) * | 1997-08-27 | 2004-06-07 | 株式会社東芝 | ストール検出表示装置及び方法 |
US6292845B1 (en) * | 1998-08-26 | 2001-09-18 | Infineon Technologies North America Corp. | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively |
US6282633B1 (en) * | 1998-11-13 | 2001-08-28 | Tensilica, Inc. | High data density RISC processor |
GB2352066B (en) * | 1999-07-14 | 2003-11-05 | Element 14 Ltd | An instruction set for a computer |
EP1208423A2 (de) * | 2000-03-10 | 2002-05-29 | Koninklijke Philips Electronics N.V. | Verfahren um ein programm zu kompilieren |
DE10043003A1 (de) | 2000-09-01 | 2002-03-14 | Infineon Technologies Ag | Programmgesteuerte Einheit |
US7328314B2 (en) * | 2002-06-19 | 2008-02-05 | Alcatel-Lucent Canada Inc. | Multiprocessor computing device having shared program memory |
US7793080B2 (en) * | 2007-12-31 | 2010-09-07 | Globalfoundries Inc. | Processing pipeline having parallel dispatch and method thereof |
US20090172370A1 (en) * | 2007-12-31 | 2009-07-02 | Advanced Micro Devices, Inc. | Eager execution in a processing pipeline having multiple integer execution units |
US8086825B2 (en) * | 2007-12-31 | 2011-12-27 | Advanced Micro Devices, Inc. | Processing pipeline having stage-specific thread selection and method thereof |
US8589950B2 (en) * | 2011-01-05 | 2013-11-19 | Blackberry Limited | Processing user input events in a web browser |
CN103336681B (zh) * | 2013-07-03 | 2015-11-25 | 同济大学 | 针对采用变长指令集的流水线结构处理器的取指方法 |
US10235232B2 (en) * | 2014-02-10 | 2019-03-19 | Via Alliance Semiconductor Co., Ltd | Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction |
CN110515658A (zh) * | 2014-07-30 | 2019-11-29 | 莫维迪厄斯有限公司 | 用于管理可变长度指令的方法和设备 |
US11314516B2 (en) * | 2018-01-19 | 2022-04-26 | Marvell Asia Pte, Ltd. | Issuing instructions based on resource conflict constraints in microprocessor |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1233270A (en) * | 1985-03-18 | 1988-02-23 | Vojin G. Oklobdzija | Register selection mechanism and organization of an instruction prefetch buffer |
US4926323A (en) * | 1988-03-03 | 1990-05-15 | Advanced Micro Devices, Inc. | Streamlined instruction processor |
-
1988
- 1988-10-07 US US07/255,105 patent/US5051885A/en not_active Expired - Lifetime
-
1989
- 1989-10-06 DE DE68927492T patent/DE68927492T2/de not_active Expired - Lifetime
- 1989-10-06 EP EP89310272A patent/EP0363222B1/de not_active Expired - Lifetime
- 1989-10-06 JP JP1261908A patent/JP2864421B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0363222A3 (de) | 1992-07-01 |
US5051885A (en) | 1991-09-24 |
JPH02224055A (ja) | 1990-09-06 |
EP0363222B1 (de) | 1996-11-27 |
DE68927492T2 (de) | 1997-04-03 |
JP2864421B2 (ja) | 1999-03-03 |
EP0363222A2 (de) | 1990-04-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE |