DE69412630D1 - Hardware-unterstützte schaltung zur übersetzung virtueller adressen und verfahren dafür - Google Patents

Hardware-unterstützte schaltung zur übersetzung virtueller adressen und verfahren dafür

Info

Publication number
DE69412630D1
DE69412630D1 DE69412630T DE69412630T DE69412630D1 DE 69412630 D1 DE69412630 D1 DE 69412630D1 DE 69412630 T DE69412630 T DE 69412630T DE 69412630 T DE69412630 T DE 69412630T DE 69412630 D1 DE69412630 D1 DE 69412630D1
Authority
DE
Germany
Prior art keywords
hardware
virtual addresses
translate virtual
assisted circuit
assisted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69412630T
Other languages
English (en)
Other versions
DE69412630T2 (de
Inventor
Stephen Olson
James Macdonald
Richard Lones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
LG Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Application granted granted Critical
Publication of DE69412630D1 publication Critical patent/DE69412630D1/de
Publication of DE69412630T2 publication Critical patent/DE69412630T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
DE69412630T 1993-10-12 1994-03-24 Hardware-unterstützte schaltung zur übersetzung virtueller adressen und verfahren dafür Expired - Lifetime DE69412630T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/135,037 US5479628A (en) 1993-10-12 1993-10-12 Virtual address translation hardware assist circuit and method
PCT/US1994/003241 WO1995010808A1 (en) 1993-10-12 1994-03-24 Virtual address translation hardware assist circuit and method

Publications (2)

Publication Number Publication Date
DE69412630D1 true DE69412630D1 (de) 1998-09-24
DE69412630T2 DE69412630T2 (de) 1999-04-15

Family

ID=22466212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69412630T Expired - Lifetime DE69412630T2 (de) 1993-10-12 1994-03-24 Hardware-unterstützte schaltung zur übersetzung virtueller adressen und verfahren dafür

Country Status (5)

Country Link
US (1) US5479628A (de)
EP (1) EP0723682B1 (de)
AU (1) AU677414B2 (de)
DE (1) DE69412630T2 (de)
WO (1) WO1995010808A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5842225A (en) * 1995-02-27 1998-11-24 Sun Microsystems, Inc. Method and apparatus for implementing non-faulting load instruction
US5630088A (en) * 1995-03-09 1997-05-13 Hewlett-Packard Company Virtual to physical address translation
US5787241A (en) * 1995-12-18 1998-07-28 Integrated Device Technology, Inc. Method and apparatus for locating exception correction routines
IL116989A (en) 1996-01-31 1999-10-28 Galileo Technology Ltd Switching ethernet controller
US5732404A (en) * 1996-03-29 1998-03-24 Unisys Corporation Flexible expansion of virtual memory addressing
JP4079506B2 (ja) * 1997-08-08 2008-04-23 株式会社東芝 不揮発性半導体メモリシステムの制御方法
US6829689B1 (en) * 2002-02-12 2004-12-07 Nvidia Corporation Method and system for memory access arbitration for minimizing read/write turnaround penalties
US20050216552A1 (en) * 2004-03-24 2005-09-29 Samuel Fineberg Communication-link-attached persistent memory system
KR101278156B1 (ko) * 2005-05-03 2013-06-28 삼성전자주식회사 디지털 방송 녹화 기기 및 이를 이용한 타이틀 기록 방법
US7657725B2 (en) * 2005-06-24 2010-02-02 Sigmatel, Inc. Integrated circuit with memory-less page table
US8276201B2 (en) * 2007-03-22 2012-09-25 International Business Machines Corporation Integrity protection in data processing systems
US9652402B2 (en) * 2014-12-23 2017-05-16 Texas Instruments Incorporated Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096568A (en) * 1976-09-24 1978-06-20 Sperry Rand Corporation Virtual address translator
US4128875A (en) * 1976-12-16 1978-12-05 Sperry Rand Corporation Optional virtual memory system
US4410941A (en) * 1980-12-29 1983-10-18 Wang Laboratories, Inc. Computer having an indexed local ram to store previously translated virtual addresses
US4654777A (en) * 1982-05-25 1987-03-31 Tokyo Shibaura Denki Kabushiki Kaisha Segmented one and two level paging address translation system
USRE37305E1 (en) * 1982-12-30 2001-07-31 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4714993A (en) * 1983-10-18 1987-12-22 International Business Machines Corporation Apparatus and method for effecting dynamic address translation in a microprocessor implemented data processing system
US4680700A (en) * 1983-12-07 1987-07-14 International Business Machines Corporation Virtual memory address translation mechanism with combined hash address table and inverted page table
AU603167B2 (en) * 1986-12-23 1990-11-08 Bull Hn Information Systems Inc. Segment descriptor unit
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
US5265227A (en) * 1989-11-14 1993-11-23 Intel Corporation Parallel protection checking in an address translation look-aside buffer

Also Published As

Publication number Publication date
EP0723682A1 (de) 1996-07-31
US5479628A (en) 1995-12-26
DE69412630T2 (de) 1999-04-15
AU7310394A (en) 1995-05-04
AU677414B2 (en) 1997-04-24
EP0723682B1 (de) 1998-08-19
WO1995010808A1 (en) 1995-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: LG ELECTRONICS INC., SEOUL/SOUL, KR

8328 Change in the person/name/address of the agent

Representative=s name: COHAUSZ & FLORACK, 40472 DUESSELDORF