DE68916106D1 - Verfahren und Gerät zur Prüfung von Tri-State-Treibern. - Google Patents

Verfahren und Gerät zur Prüfung von Tri-State-Treibern.

Info

Publication number
DE68916106D1
DE68916106D1 DE68916106T DE68916106T DE68916106D1 DE 68916106 D1 DE68916106 D1 DE 68916106D1 DE 68916106 T DE68916106 T DE 68916106T DE 68916106 T DE68916106 T DE 68916106T DE 68916106 D1 DE68916106 D1 DE 68916106D1
Authority
DE
Germany
Prior art keywords
state drivers
tri
testing
testing tri
drivers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916106T
Other languages
English (en)
Other versions
DE68916106T2 (de
Inventor
Patricia Karen Graham
Robert Russell Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68916106D1 publication Critical patent/DE68916106D1/de
Application granted granted Critical
Publication of DE68916106T2 publication Critical patent/DE68916106T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
DE68916106T 1988-04-29 1989-03-14 Verfahren und Gerät zur Prüfung von Tri-State-Treibern. Expired - Fee Related DE68916106T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/187,703 US4841232A (en) 1988-04-29 1988-04-29 Method and apparatus for testing three state drivers

Publications (2)

Publication Number Publication Date
DE68916106D1 true DE68916106D1 (de) 1994-07-21
DE68916106T2 DE68916106T2 (de) 1995-01-12

Family

ID=22690113

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916106T Expired - Fee Related DE68916106T2 (de) 1988-04-29 1989-03-14 Verfahren und Gerät zur Prüfung von Tri-State-Treibern.

Country Status (4)

Country Link
US (1) US4841232A (de)
EP (1) EP0340137B1 (de)
JP (1) JPH0792494B2 (de)
DE (1) DE68916106T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476596A (en) * 1987-09-18 1989-03-22 Oki Electric Ind Co Ltd Error of eeprom detecting device
US5498972A (en) * 1990-08-15 1996-03-12 Telefonaktiebolaget Lm Ericsson Device for monitoring the supply voltage on integrated circuits
US5159273A (en) * 1990-09-28 1992-10-27 Hughes Aircraft Company Tri-state bus driver to support reconfigurable fault tolerant logic
US5359606A (en) * 1992-02-12 1994-10-25 Storage Technology Corporation Data quality analysis in a data signal processing channel
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
EP0667533A3 (de) * 1994-02-14 1996-06-12 Hewlett Packard Co Signalverlustdetektor.
US5572535A (en) * 1994-07-05 1996-11-05 Motorola Inc. Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design
US5583448A (en) * 1994-11-14 1996-12-10 New Media Corp. System bus termination status detection
JPH09160690A (ja) * 1995-12-08 1997-06-20 Nec Corp バスドライバ故障検出方式
US5867644A (en) * 1996-09-10 1999-02-02 Hewlett Packard Company System and method for on-chip debug support and performance monitoring in a microprocessor
US5887003A (en) * 1996-09-10 1999-03-23 Hewlett-Packard Company Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results
US5881224A (en) * 1996-09-10 1999-03-09 Hewlett-Packard Company Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle
US6003107A (en) * 1996-09-10 1999-12-14 Hewlett-Packard Company Circuitry for providing external access to signals that are internal to an integrated circuit chip package
US5956476A (en) * 1996-10-31 1999-09-21 Hewlett Packard Company Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns
US5956477A (en) * 1996-11-25 1999-09-21 Hewlett-Packard Company Method for processing information in a microprocessor to facilitate debug and performance monitoring
US6009539A (en) * 1996-11-27 1999-12-28 Hewlett-Packard Company Cross-triggering CPUs for enhanced test operations in a multi-CPU computer system
US5881217A (en) * 1996-11-27 1999-03-09 Hewlett-Packard Company Input comparison circuitry and method for a programmable state machine
JPH11237454A (ja) * 1998-02-20 1999-08-31 Advantest Corp 半導体試験装置
US5999013A (en) * 1998-04-15 1999-12-07 International Business Machines Corporation Method and apparatus for testing variable voltage and variable impedance drivers
US6374370B1 (en) 1998-10-30 2002-04-16 Hewlett-Packard Company Method and system for flexible control of BIST registers based upon on-chip events
US6425025B1 (en) 1999-06-03 2002-07-23 Dell Usa, L.P. System and method for connecting electronic circuitry in a computer system
US6754867B2 (en) 2000-12-28 2004-06-22 Intel Corporation Method of determining non-accessible device I/O pin speed using on chip LFSR and MISR as data source and results analyzer respectively
US8699356B2 (en) * 2010-12-20 2014-04-15 Deere & Company Method and system for diagnosing a fault or open circuit in a network

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849726A (en) * 1974-01-28 1974-11-19 Sperry Rand Corp Universal programmable digital testing interface line
JPS5413888U (de) * 1977-06-30 1979-01-29
US4242751A (en) * 1978-08-28 1980-12-30 Genrad, Inc. Automatic fault-probing method and apparatus for checking electrical circuits and the like
US4236246A (en) * 1978-11-03 1980-11-25 Genrad, Inc. Method of and apparatus for testing electronic circuit assemblies and the like
DE3173631D1 (en) * 1981-09-10 1986-03-13 Ibm Deutschland Procedure and circuit arrangement for checking a circuit which is integrated with a three-state driver, which is driven to high impedance by this circuit
US4459693A (en) * 1982-01-26 1984-07-10 Genrad, Inc. Method of and apparatus for the automatic diagnosis of the failure of electrical devices connected to common bus nodes and the like
US4475195A (en) * 1982-04-01 1984-10-02 Honeywell Information Systems Inc. Apparatus for microprocessor address bus testing
US4514845A (en) * 1982-08-23 1985-04-30 At&T Bell Laboratories Method and apparatus for bus fault location
JPS5975167A (ja) * 1982-10-25 1984-04-27 Hitachi Ltd 論理回路テスト方式
US4528505A (en) * 1983-03-29 1985-07-09 Motorola, Inc. On chip voltage monitor and method for using same

Also Published As

Publication number Publication date
EP0340137A2 (de) 1989-11-02
EP0340137B1 (de) 1994-06-15
DE68916106T2 (de) 1995-01-12
JPH0213865A (ja) 1990-01-18
US4841232A (en) 1989-06-20
JPH0792494B2 (ja) 1995-10-09
EP0340137A3 (de) 1991-08-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee