DE60231266D1 - Schaltung zur Daten-und Taktrückgewinnung - Google Patents

Schaltung zur Daten-und Taktrückgewinnung

Info

Publication number
DE60231266D1
DE60231266D1 DE60231266T DE60231266T DE60231266D1 DE 60231266 D1 DE60231266 D1 DE 60231266D1 DE 60231266 T DE60231266 T DE 60231266T DE 60231266 T DE60231266 T DE 60231266T DE 60231266 D1 DE60231266 D1 DE 60231266D1
Authority
DE
Germany
Prior art keywords
circuit
data
clock recovery
clock
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60231266T
Other languages
English (en)
Inventor
Keiji Kishine
Haruhiko Ichino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Application granted granted Critical
Publication of DE60231266D1 publication Critical patent/DE60231266D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/04Distributors combined with modulators or demodulators
    • H04J3/047Distributors with transistors or integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
DE60231266T 2001-03-07 2002-03-05 Schaltung zur Daten-und Taktrückgewinnung Expired - Lifetime DE60231266D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001063775 2001-03-07
JP2001326090 2001-10-24

Publications (1)

Publication Number Publication Date
DE60231266D1 true DE60231266D1 (de) 2009-04-09

Family

ID=26610796

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60231266T Expired - Lifetime DE60231266D1 (de) 2001-03-07 2002-03-05 Schaltung zur Daten-und Taktrückgewinnung

Country Status (4)

Country Link
US (1) US7095816B2 (de)
EP (1) EP1239627B1 (de)
CA (1) CA2374777C (de)
DE (1) DE60231266D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4426739B2 (ja) * 2001-06-26 2010-03-03 日本オプネクスト株式会社 光モジュールおよびその製造方法
DE10132403A1 (de) * 2001-07-09 2003-01-23 Alcatel Sa Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal
US6862397B2 (en) * 2002-10-15 2005-03-01 The Boeing Company Method for audibly measuring optical efficiency in an installed fiber optic link
EP1471667B1 (de) * 2003-04-22 2005-09-07 Alcatel Taktrückgewinnung von verzerrten optischen Signalen
DE102004047871A1 (de) * 2004-10-01 2006-04-06 Deutsche Thomson-Brandt Gmbh Signal-Eingangsschaltung
KR100607858B1 (ko) * 2004-12-31 2006-08-08 삼성전자주식회사 이동통신단말기에서 사용주파수 대역의 잡음을 제거하기위한 장치 및 방법
US7861105B2 (en) * 2007-06-25 2010-12-28 Analogix Semiconductor, Inc. Clock data recovery (CDR) system using interpolator and timing loop module
JP2009094638A (ja) * 2007-10-04 2009-04-30 Yokogawa Electric Corp 高周波モジュール
WO2012070073A1 (en) * 2010-11-23 2012-05-31 Power-One Italy S.P.A. Method and circuit for clock recovery of a data stream description
US8755480B1 (en) * 2011-12-30 2014-06-17 Altera Corporation Integrated circuit (IC) clocking techniques
EP2755350A1 (de) * 2013-01-15 2014-07-16 Alcatel-Lucent Vorrichtung zur Ausführung von Takt- und/oder Daten-Rückgewinnung
US9166605B2 (en) * 2013-03-18 2015-10-20 Terasquare Co., Ltd. Low-power and all-digital phase interpolator-based clock and data recovery architecture
US10212006B2 (en) * 2016-03-01 2019-02-19 Mediatek Inc. Feed-forward filtering device and associated method
KR102653891B1 (ko) 2016-11-30 2024-04-02 삼성전자주식회사 지연 클록 신호의 위상을 보간하기 위한 위상 보간기 및 이를 포함하고, 위상이 보간된 클록 신호를 이용하여 데이터 샘플링을 수행하는 장치
CN108322212A (zh) * 2018-05-14 2018-07-24 广东工业大学 一种高速低功耗四/五预分频器
TWI768690B (zh) * 2021-01-29 2022-06-21 瑞昱半導體股份有限公司 無參考時脈之時脈資料回復裝置及其方法
CN113300702B (zh) * 2021-05-24 2023-03-24 成都振芯科技股份有限公司 一种信号抖动分离电路及方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0693667B2 (ja) * 1988-08-03 1994-11-16 富士通株式会社 同期多重方式
JPH0556410A (ja) 1991-08-28 1993-03-05 Fujitsu General Ltd テレビ受信機
JP3196949B2 (ja) 1993-02-23 2001-08-06 日本電信電話株式会社 データ信号位相比較回路
JP3481051B2 (ja) * 1996-06-19 2003-12-22 富士通株式会社 チャージポンプ回路、および、該チャージポンプ回路を有するpll回路並びに半導体集積回路
JP2862078B2 (ja) 1996-10-18 1999-02-24 日本電気株式会社 Pll
US5933058A (en) * 1996-11-22 1999-08-03 Zoran Corporation Self-tuning clock recovery phase-locked loop circuit
JP2993559B2 (ja) * 1997-03-31 1999-12-20 日本電気株式会社 位相同期回路
JP3385577B2 (ja) 1997-08-07 2003-03-10 日本電信電話株式会社 電圧制御発振器及びpll回路
US6178213B1 (en) * 1998-08-25 2001-01-23 Vitesse Semiconductor Corporation Adaptive data recovery system and methods
AU1607400A (en) * 1998-11-03 2000-05-22 Broadcom Corporation Dual mode qam/vsb receiver
CA2293173A1 (en) * 1999-12-29 2001-06-29 Nortel Networks Corporation Agile phase noise filter using vcxo and frequency synthesis
US6359519B1 (en) * 2000-02-11 2002-03-19 Agere Systems Guardian Corp. Self-timed numerically controlled ring oscillator
JP4246965B2 (ja) * 2002-05-31 2009-04-02 株式会社日立製作所 半導体集積回路装置

Also Published As

Publication number Publication date
EP1239627A3 (de) 2005-11-30
EP1239627A2 (de) 2002-09-11
US20020159556A1 (en) 2002-10-31
CA2374777A1 (en) 2002-09-07
CA2374777C (en) 2004-05-25
EP1239627B1 (de) 2009-02-25
US7095816B2 (en) 2006-08-22

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