DE602006012833D1 - Substrate zur verhinderung von wellungen und herstellungsverfahren dafür - Google Patents
Substrate zur verhinderung von wellungen und herstellungsverfahren dafürInfo
- Publication number
- DE602006012833D1 DE602006012833D1 DE602006012833T DE602006012833T DE602006012833D1 DE 602006012833 D1 DE602006012833 D1 DE 602006012833D1 DE 602006012833 T DE602006012833 T DE 602006012833T DE 602006012833 T DE602006012833 T DE 602006012833T DE 602006012833 D1 DE602006012833 D1 DE 602006012833D1
- Authority
- DE
- Germany
- Prior art keywords
- feature
- wellungen
- substrates
- preventing
- manufacturing process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Liquid Crystal (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electronic Switches (AREA)
- Combinations Of Printed Boards (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69364805P | 2005-06-24 | 2005-06-24 | |
PCT/IB2006/052067 WO2006137043A1 (en) | 2005-06-24 | 2006-06-23 | Warpage preventing substrates and method of making same |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006012833D1 true DE602006012833D1 (de) | 2010-04-22 |
Family
ID=37309487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006012833T Active DE602006012833D1 (de) | 2005-06-24 | 2006-06-23 | Substrate zur verhinderung von wellungen und herstellungsverfahren dafür |
Country Status (7)
Country | Link |
---|---|
US (1) | US8383954B2 (de) |
EP (1) | EP1897424B1 (de) |
JP (1) | JP4913134B2 (de) |
CN (1) | CN101204124B (de) |
AT (1) | ATE460829T1 (de) |
DE (1) | DE602006012833D1 (de) |
WO (1) | WO2006137043A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014229761A (ja) * | 2013-05-23 | 2014-12-08 | 株式会社東芝 | 電子機器 |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4104111A (en) * | 1977-08-03 | 1978-08-01 | Mack Robert L | Process for manufacturing printed circuit boards |
US4426767A (en) * | 1982-01-11 | 1984-01-24 | Sperry Cororation | Selective epitaxial etch planar processing for gallium arsenide semiconductors |
US4512829A (en) * | 1983-04-07 | 1985-04-23 | Satosen Co., Ltd. | Process for producing printed circuit boards |
US4487654A (en) * | 1983-10-27 | 1984-12-11 | Ael Microtel Limited | Method of manufacturing printed wiring boards |
US4720324A (en) * | 1985-10-03 | 1988-01-19 | Hayward John S | Process for manufacturing printed circuit boards |
DE3629177A1 (de) * | 1986-08-28 | 1988-03-17 | Hoechst Ag | Vernetzte polymerisate und verfahren zu ihrer herstellung |
DE3811042A1 (de) * | 1988-03-31 | 1989-10-19 | Merck Patent Gmbh | Ionenaustauscher |
US4842699A (en) * | 1988-05-10 | 1989-06-27 | Avantek, Inc. | Method of selective via-hole and heat sink plating using a metal mask |
US5038132A (en) * | 1989-12-22 | 1991-08-06 | Texas Instruments Incorporated | Dual function circuit board, a resistor element therefor, and a circuit embodying the element |
DE9013137U1 (de) * | 1990-09-15 | 1992-01-23 | Röhm GmbH, 6100 Darmstadt | Hochvernetztes, perlförmiges, aktivierbares, hydrophiles Trägermaterial |
US5160579A (en) * | 1991-06-05 | 1992-11-03 | Macdermid, Incorporated | Process for manufacturing printed circuit employing selective provision of solderable coating |
JP3366062B2 (ja) * | 1992-07-02 | 2003-01-14 | モトローラ・インコーポレイテッド | オーバモールド形半導体装置及びその製造方法 |
EP0584386A1 (de) * | 1992-08-26 | 1994-03-02 | International Business Machines Corporation | Leiterplatte und Herstellungsverfahren für Leiterplatten |
WO1994018701A1 (en) | 1993-02-05 | 1994-08-18 | W.L. Gore & Associates, Inc. | Stress-resistant semiconductor chip-circuit board interconnect |
US5872338A (en) * | 1996-04-10 | 1999-02-16 | Prolinx Labs Corporation | Multilayer board having insulating isolation rings |
US6011694A (en) | 1996-08-01 | 2000-01-04 | Fuji Machinery Mfg. & Electronics Co., Ltd. | Ball grid array semiconductor package with solder ball openings in an insulative base |
JPH11186432A (ja) | 1997-12-25 | 1999-07-09 | Canon Inc | 半導体パッケージ及びその製造方法 |
US6034427A (en) * | 1998-01-28 | 2000-03-07 | Prolinx Labs Corporation | Ball grid array structure and method for packaging an integrated circuit chip |
US6565954B2 (en) * | 1998-05-14 | 2003-05-20 | Matsushita Electric Industrial Co., Ltd. | Circuit board and method of manufacturing the same |
US6711812B1 (en) * | 1999-04-13 | 2004-03-30 | Unicap Electronics Industrial Corporation | Method of making metal core substrate printed circuit wiring board enabling thermally enhanced ball grid array (BGA) packages |
DE19920794A1 (de) * | 1999-05-06 | 2000-11-09 | Merck Patent Gmbh | Verfahren zur Herstellung von Perlpolymerisaten |
US6351393B1 (en) * | 1999-07-02 | 2002-02-26 | International Business Machines Corporation | Electronic package for electronic components and method of making same |
US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
JP2001267463A (ja) * | 2000-03-17 | 2001-09-28 | Nec Yamaguchi Ltd | 半導体装置基板及び半導体装置の製造方法 |
US6573610B1 (en) * | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
DE10042764A1 (de) | 2000-08-31 | 2002-03-14 | Moeller Gmbh | Verfahren zur Herstellung eines massereichen ohmschen Widerstands und elektronische Baueinheit |
JP4923336B2 (ja) * | 2001-04-10 | 2012-04-25 | 日本電気株式会社 | 回路基板及び該回路基板を用いた電子機器 |
JP2003087094A (ja) * | 2001-07-02 | 2003-03-20 | Toshiba Corp | 弾性表面波装置及びその製造方法 |
US6768064B2 (en) * | 2001-07-10 | 2004-07-27 | Fujikura Ltd. | Multilayer wiring board assembly, multilayer wiring board assembly component and method of manufacture thereof |
TW508703B (en) | 2001-10-09 | 2002-11-01 | Advanced Semiconductor Eng | Manufacturing method of semiconductor chip package structure |
JP2003124387A (ja) * | 2001-10-10 | 2003-04-25 | Sony Corp | 半導体装置及び該半導体装置に使用されるプリント基板 |
JP2003332490A (ja) * | 2002-05-17 | 2003-11-21 | Tdk Corp | 部品搭載基板、及び、これを用いた電子部品 |
TW564533B (en) * | 2002-10-08 | 2003-12-01 | Siliconware Precision Industries Co Ltd | Warpage-preventing substrate |
TWI229574B (en) * | 2002-11-05 | 2005-03-11 | Siliconware Precision Industries Co Ltd | Warpage-preventing circuit board and method for fabricating the same |
US6896173B2 (en) * | 2003-07-21 | 2005-05-24 | Via Technologies, Inc. | Method of fabricating circuit substrate |
-
2006
- 2006-06-23 CN CN2006800225244A patent/CN101204124B/zh active Active
- 2006-06-23 JP JP2008517691A patent/JP4913134B2/ja active Active
- 2006-06-23 DE DE602006012833T patent/DE602006012833D1/de active Active
- 2006-06-23 US US11/917,613 patent/US8383954B2/en active Active
- 2006-06-23 WO PCT/IB2006/052067 patent/WO2006137043A1/en active Application Filing
- 2006-06-23 AT AT06765851T patent/ATE460829T1/de not_active IP Right Cessation
- 2006-06-23 EP EP06765851A patent/EP1897424B1/de active Active
Also Published As
Publication number | Publication date |
---|---|
EP1897424B1 (de) | 2010-03-10 |
JP4913134B2 (ja) | 2012-04-11 |
WO2006137043A1 (en) | 2006-12-28 |
EP1897424A1 (de) | 2008-03-12 |
CN101204124B (zh) | 2013-01-02 |
JP2008547215A (ja) | 2008-12-25 |
CN101204124A (zh) | 2008-06-18 |
ATE460829T1 (de) | 2010-03-15 |
US20090103274A1 (en) | 2009-04-23 |
US8383954B2 (en) | 2013-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |