DE60031596D1 - Zeitmultiplex-Vermittlungssystem (TDM) mit sehr breitem Speicher - Google Patents

Zeitmultiplex-Vermittlungssystem (TDM) mit sehr breitem Speicher

Info

Publication number
DE60031596D1
DE60031596D1 DE60031596T DE60031596T DE60031596D1 DE 60031596 D1 DE60031596 D1 DE 60031596D1 DE 60031596 T DE60031596 T DE 60031596T DE 60031596 T DE60031596 T DE 60031596T DE 60031596 D1 DE60031596 D1 DE 60031596D1
Authority
DE
Germany
Prior art keywords
packets
width
packet
system includes
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60031596T
Other languages
English (en)
Other versions
DE60031596T2 (de
Inventor
Ronald P Bianchini Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ericsson AB
Original Assignee
Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson AB filed Critical Ericsson AB
Publication of DE60031596D1 publication Critical patent/DE60031596D1/de
Application granted granted Critical
Publication of DE60031596T2 publication Critical patent/DE60031596T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103—Memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13292—Time division multiplexing, TDM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13299—Bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
DE60031596T 1999-04-15 2000-04-06 Zeitmultiplex-Vermittlungssystem (TDM) mit sehr breitem Speicher Expired - Lifetime DE60031596T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US293563 1999-04-15
US09/293,563 US7031330B1 (en) 1999-04-15 1999-04-15 Very wide memory TDM switching system

Publications (2)

Publication Number Publication Date
DE60031596D1 true DE60031596D1 (de) 2006-12-14
DE60031596T2 DE60031596T2 (de) 2007-09-06

Family

ID=23129591

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60031596T Expired - Lifetime DE60031596T2 (de) 1999-04-15 2000-04-06 Zeitmultiplex-Vermittlungssystem (TDM) mit sehr breitem Speicher

Country Status (5)

Country Link
US (1) US7031330B1 (de)
EP (1) EP1045558B1 (de)
JP (1) JP4480845B2 (de)
AT (1) ATE344560T1 (de)
DE (1) DE60031596T2 (de)

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GB2381407B (en) * 2001-10-24 2004-06-30 Zarlink Semiconductor Ltd Dynamic buffering in packet systems
US7408957B2 (en) * 2002-06-13 2008-08-05 International Business Machines Corporation Selective header field dispatch in a network processing system
GB2396447A (en) * 2002-12-21 2004-06-23 Robert Clive Roust Data flow processing technique
US7492760B1 (en) * 2003-03-31 2009-02-17 Pmc-Sierra, Inc. Memory egress self selection architecture
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US8624906B2 (en) * 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8683184B1 (en) 2004-11-15 2014-03-25 Nvidia Corporation Multi context execution on a video processor
US8072887B1 (en) * 2005-02-07 2011-12-06 Extreme Networks, Inc. Methods, systems, and computer program products for controlling enqueuing of packets in an aggregated queue including a plurality of virtual queues using backpressure messages from downstream queues
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US7852866B2 (en) * 2006-12-29 2010-12-14 Polytechnic Institute of New York Universiity Low complexity scheduling algorithm for a buffered crossbar switch with 100% throughput
US7978690B2 (en) * 2007-03-31 2011-07-12 International Business Machines Corporation Method to operate a crossbar switch
US8683126B2 (en) 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8780123B2 (en) 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8923385B2 (en) 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8681861B2 (en) 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8489851B2 (en) 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US8452908B2 (en) * 2009-12-29 2013-05-28 Juniper Networks, Inc. Low latency serial memory interface
EP2552123B1 (de) * 2010-03-24 2019-12-18 Nec Corporation Übertragungsvorrichtung und übertragungsverfahren
US8824491B2 (en) * 2010-10-25 2014-09-02 Polytechnic Institute Of New York University Distributed scheduling for variable-size packet switching system
US9039432B2 (en) 2011-07-08 2015-05-26 Cisco Technology, Inc. System and method for high connectivity platform
US8545246B2 (en) 2011-07-25 2013-10-01 Cisco Technology, Inc. High connectivity platform
CN111724804A (zh) * 2020-06-29 2020-09-29 北京百度网讯科技有限公司 用于处理信息的方法和装置

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US5233603A (en) * 1988-04-21 1993-08-03 Nec Corporation Packet switch suitable for integrated circuit implementation
US5475680A (en) * 1989-09-15 1995-12-12 Gpt Limited Asynchronous time division multiplex switching system
FR2666472B1 (fr) * 1990-08-31 1992-10-16 Alcatel Nv Systeme de memorisation temporaire d'information comprenant une memoire tampon enregistrant des donnees en blocs de donnees de longueur fixe ou variable.
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
US5309432A (en) * 1992-05-06 1994-05-03 At&T Bell Laboratories High-speed packet switch
US5732041A (en) * 1993-08-19 1998-03-24 Mmc Networks, Inc. Memory interface unit, shared memory switch system and associated method
JPH08288965A (ja) * 1995-04-18 1996-11-01 Hitachi Ltd スイッチングシステム
JP2856104B2 (ja) * 1995-04-18 1999-02-10 日本電気株式会社 Ａｔｍスイッチ
US5574505A (en) * 1995-05-16 1996-11-12 Thomson Multimedia S.A. Method and apparatus for operating a transport stream encoder to produce a stream of packets carrying data representing a plurality of component signals
US5991295A (en) * 1995-10-10 1999-11-23 Madge Networks Limited Digital switch
JP2827998B2 (ja) * 1995-12-13 1998-11-25 日本電気株式会社 Ａｔｍ交換方法
US5802052A (en) * 1996-06-26 1998-09-01 Level One Communication, Inc. Scalable high performance switch element for a shared memory packet or ATM cell switch fabric
JPH10126419A (ja) * 1996-10-23 1998-05-15 Nec Corp Ａｔｍ交換機システム
US6061358A (en) * 1997-02-13 2000-05-09 Mcdata Corporation Data communication system utilizing a scalable, non-blocking, high bandwidth central memory controller and method
US6034957A (en) * 1997-08-29 2000-03-07 Extreme Networks, Inc. Sliced comparison engine architecture and method for a LAN switch
JP3566047B2 (ja) * 1997-10-17 2004-09-15 富士通株式会社 ネットワークシステム及び通信装置
US6137807A (en) * 1997-12-05 2000-10-24 Whittaker Corporation Dual bank queue memory and queue control system
US6470021B1 (en) * 1998-01-27 2002-10-22 Alcatel Internetworking (Pe), Inc. Computer network switch with parallel access shared memory architecture

Also Published As

Publication number Publication date
EP1045558A3 (de) 2004-11-17
US7031330B1 (en) 2006-04-18
ATE344560T1 (de) 2006-11-15
JP4480845B2 (ja) 2010-06-16
JP2000349789A (ja) 2000-12-15
EP1045558A2 (de) 2000-10-18
EP1045558B1 (de) 2006-11-02
DE60031596T2 (de) 2007-09-06

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